CONFIG_CLOCK_STM32_PLL_PREDIV1

PREDIV1 Prescaler

PREDIV1 Prescaler

Type: int

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PREDIV is PLLSCR clock signal prescaler, present on STM32F0 SoC having an HSE Oscillator available like the stm32f04xx, stm32f07xx, stm32f09xx and stm32f030xc parts. If configured on a non supported part, the HSI oscillator will be used a default PLL source and this config will be ignored. Allowed values: 1 - 16.

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PREDIV1 is PLL clock signal prescaler, allowed values: 1 - 16.

Kconfig definitions

At drivers/clock_control/Kconfig.stm32:127

Included via Kconfig:10Kconfig.zephyr:35drivers/Kconfig:54drivers/clock_control/Kconfig:30

Menu path: (top menu) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_PREDIV1
    int
    prompt "PREDIV1 Prescaler" if CLOCK_STM32_PLL_SRC_HSE && SOC_SERIES_STM32F0X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    range 1 16 if CLOCK_STM32_PLL_SRC_HSE && SOC_SERIES_STM32F0X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    default 1 if CLOCK_STM32_PLL_SRC_HSE && SOC_SERIES_STM32F0X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    depends on CLOCK_STM32_PLL_SRC_HSE && SOC_SERIES_STM32F0X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PREDIV is PLLSCR clock signal prescaler, present on STM32F0 SoC having
      an HSE Oscillator available like the stm32f04xx, stm32f07xx,
      stm32f09xx and stm32f030xc parts. If configured on a non supported
      part, the HSI oscillator will be used a default PLL source and this
      config will be ignored.
      Allowed values: 1 - 16.

At drivers/clock_control/Kconfig.stm32:169

Included via Kconfig:10Kconfig.zephyr:35drivers/Kconfig:54drivers/clock_control/Kconfig:30

Menu path: (top menu) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_PREDIV1
    int
    prompt "PREDIV1 Prescaler" if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F1X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    range 1 16 if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F1X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    default 1 if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F1X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F1X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PREDIV1 is PLL clock signal prescaler, allowed values: 1 - 16.

(Definitions include propagated dependencies, including from if’s and menus.)