CONFIG_CLOCK_STM32_PLL_M_DIVISOR

Division factor for PLL VCO input clock

Division factor for PLL VCO input clock

PLL divisor

Type: int

Help

PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63

Help

PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63

Help

PLL divisor, allowed values: 1-8. With this ensure that the PLL VCO input frequency ranges from 4 to 16MHz.

Kconfig definitions

At boards/arm/disco_l475_iot1/Kconfig.defconfig:45

Included via Kconfig:10Kconfig.zephyr:21

Menu path: (top menu)

config CLOCK_STM32_PLL_M_DIVISOR
    int
    default 1 if CLOCK_STM32_PLL_SRC_HSI && CLOCK_STM32_SYSCLK_SRC_PLL && BOARD_DISCO_L475_IOT1
    depends on CLOCK_STM32_PLL_SRC_HSI && CLOCK_STM32_SYSCLK_SRC_PLL && BOARD_DISCO_L475_IOT1

At drivers/clock_control/Kconfig.stm32:197

Included via Kconfig:10Kconfig.zephyr:35drivers/Kconfig:54drivers/clock_control/Kconfig:30

Menu path: (top menu) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_M_DIVISOR
    int
    prompt "Division factor for PLL VCO input clock" if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    range 2 63 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    default 20 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PLLM division factor needs to be set correctly to ensure that the VCO
      input frequency ranges from 1 to 2 MHz. It is recommended to select a
      frequency of 2 MHz to limit PLL jitter.
      Allowed values: 2-63

At drivers/clock_control/Kconfig.stm32:259

Included via Kconfig:10Kconfig.zephyr:35drivers/Kconfig:54drivers/clock_control/Kconfig:30

Menu path: (top menu) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_M_DIVISOR
    int
    prompt "Division factor for PLL VCO input clock" if CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    range 2 63 if CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    default 8 if CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PLLM division factor needs to be set correctly to ensure that the VCO
      input frequency ranges from 1 to 2 MHz. It is recommended to select a
      frequency of 2 MHz to limit PLL jitter.
      Allowed values: 2-63

At drivers/clock_control/Kconfig.stm32:326

Included via Kconfig:10Kconfig.zephyr:35drivers/Kconfig:54drivers/clock_control/Kconfig:30

Menu path: (top menu) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_M_DIVISOR
    int
    prompt "PLL divisor" if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    range 1 8 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    default 1 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PLL divisor, allowed values: 1-8. With this ensure that the PLL
      VCO input frequency ranges from 4 to 16MHz.

(Definitions include propagated dependencies, including from if’s and menus.)