Zephyr support status on ARC processors
Overview
This page describes current state of Zephyr for ARC processors and some future plans. Please note that
plans are given without exact deadlines
software features require corresponding hardware to be present and configured the proper way
not all the features can be enabled at the same time
Support status
Legend: Y - yes, supported; N - no, not supported; WIP - Work In Progress; TBD - to be decided
Processor families |
|||||
EM |
HS3x/4x |
VPX |
HS5x |
HS6x |
|
Port status |
upstreamed |
upstreamed |
upstreamed [6] |
upstreamed |
upstreamed |
Features |
|||||
Closely coupled memories (ICCM, DCCM) [1] |
Y |
Y |
Y |
TBD |
TBD |
Execution with caches - Instruction/Data, L1/L2 caches |
Y |
Y |
Y |
Y |
Y |
Hardware-assisted unaligned memory access |
Y [2] |
Y |
Y |
Y |
Y |
Regular interrupts with multiple priority levels, direct interrupts |
Y |
Y |
Y |
Y |
Y |
Fast interrupts, separate register banks for fast interrupts |
Y |
Y |
TBD |
N |
N |
Hardware floating point unit (FPU) |
Y |
Y |
TBD [6] |
TBD |
TBD |
Symmetric multiprocessing (SMP) support, switch-based |
N/A |
Y |
TBD |
Y |
Y |
Hardware-assisted stack checking |
Y |
Y |
Y |
N |
N |
Hardware-assisted atomic operations |
N/A |
Y |
Y |
Y |
Y |
DSP ISA |
Y |
N [3] |
TBD [6] |
TBD |
TBD |
DSP AGU/XY extensions |
Y |
N [3] |
N/A |
TBD |
TBD |
Userspace |
Y |
Y |
N |
TBD |
TBD |
Memory protection unit (MPU) |
Y |
Y |
TBD |
N |
N |
Memory management unit (MMU) |
N/A |
N |
TBD |
N |
N |
SecureShield |
Y |
N/A |
N/A |
N/A |
N/A |
Single-thread kernel support [5] |
Y |
Y |
Y |
Y |
Y |
Toolchains |
|||||
GNU (open source GCC-based) |
Y |
Y |
N |
Y |
Y |
MetaWare (proprietary Clang-based) |
Y |
Y |
Y |
Y |
Y |
Simulators |
|||||
QEMU (open source) [4] |
Y |
Y |
N |
Y |
Y |
nSIM (proprietary, provided by MetaWare Development Tools) |
Y |
Y |
Y |
Y |
Y |