Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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mpu.h
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1/*
2 * Copyright (c) 2023 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <stdint.h>
8
9#include <zephyr/toolchain.h>
11
12#include <xtensa/config/core-isa.h>
13
14#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MPU_H
15#define ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MPU_H
16
24#define XTENSA_MPU_NUM_ENTRIES XCHAL_MPU_ENTRIES
25
35#define XTENSA_MPU_ACCESS_P_NA_U_NA (0)
36
38#define XTENSA_MPU_ACCESS_P_X_U_NA (2)
39
41#define XTENSA_MPU_ACCESS_P_NA_U_X (3)
42
44#define XTENSA_MPU_ACCESS_P_RO_U_NA (4)
45
47#define XTENSA_MPU_ACCESS_P_RX_U_NA (5)
48
50#define XTENSA_MPU_ACCESS_P_RW_U_NA (6)
51
53#define XTENSA_MPU_ACCESS_P_RWX_U_NA (7)
54
56#define XTENSA_MPU_ACCESS_P_WO_U_WO (8)
57
59#define XTENSA_MPU_ACCESS_P_RW_U_RWX (9)
60
62#define XTENSA_MPU_ACCESS_P_RW_U_RO (10)
63
65#define XTENSA_MPU_ACCESS_P_RWX_U_RX (11)
66
68#define XTENSA_MPU_ACCESS_P_RO_U_RO (12)
69
71#define XTENSA_MPU_ACCESS_P_RX_U_RX (13)
72
74#define XTENSA_MPU_ACCESS_P_RW_U_RW (14)
75
77#define XTENSA_MPU_ACCESS_P_RWX_U_RWX (15)
78
95 union {
98
100 struct {
108
122
125
133 } p;
134 } as;
135
141 union {
144
146 struct {
149
152
162
176
179 } p;
180 } at;
181};
182
191};
192
199
201{
202 bool is_exec;
203
204 switch (access_rights) {
213 is_exec = true;
214 break;
215 default:
216 is_exec = false;
217 break;
218 };
219
220 return is_exec;
221}
222
224{
225 bool is_writable;
226
227 switch (access_rights) {
236 is_writable = true;
237 break;
238 default:
239 is_writable = false;
240 break;
241 };
242
243 return is_writable;
244}
245
246#define K_MEM_PARTITION_IS_EXECUTABLE(access_rights) \
247 (xtensa_mem_partition_is_executable(access_rights))
248
249#define K_MEM_PARTITION_IS_WRITABLE(access_rights) \
250 (xtensa_mem_partition_is_writable(access_rights))
251
252/* Read-Write access permission attributes */
253#define K_MEM_PARTITION_P_RW_U_RW \
254 ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RW_U_RW})
255#define K_MEM_PARTITION_P_RW_U_NA \
256 ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RW_U_NA})
257#define K_MEM_PARTITION_P_RO_U_RO \
258 ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RO_U_RO})
259#define K_MEM_PARTITION_P_RO_U_NA \
260 ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RO_U_NA})
261#define K_MEM_PARTITION_P_NA_U_NA \
262 ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_NA_U_NA})
263
264/* Execution-allowed attributes */
265#define K_MEM_PARTITION_P_RX_U_RX \
266 ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RX_U_RX})
267
278
285
288
297} __packed;
298
306extern const struct xtensa_mpu_range xtensa_soc_mpu_ranges[];
307
313extern const int xtensa_soc_mpu_ranges_num;
314
321
326#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MPU_H */
#define XTENSA_MPU_ACCESS_P_RW_U_NA
Kernel mode read and write.
Definition: mpu.h:50
#define XTENSA_MPU_ACCESS_P_RWX_U_RX
Kernel mode read, write and execution.
Definition: mpu.h:65
void xtensa_mpu_init(void)
Initialize hardware MPU.
#define XTENSA_MPU_ACCESS_P_WO_U_WO
Kernel and user modes write only.
Definition: mpu.h:56
#define XTENSA_MPU_ACCESS_P_RWX_U_RWX
Kernel and user modes read, write and execution.
Definition: mpu.h:77
static bool xtensa_mem_partition_is_writable(k_mem_partition_attr_t access_rights)
Definition: mpu.h:223
#define XTENSA_MPU_ACCESS_P_RW_U_RO
Kernel mode read and write.
Definition: mpu.h:62
const int xtensa_soc_mpu_ranges_num
Number of SoC additional memory regions.
#define XTENSA_MPU_ACCESS_P_RW_U_RW
Kernel and user modes read and write.
Definition: mpu.h:74
uint32_t k_mem_partition_attr_t
Definition: mpu.h:198
#define XTENSA_MPU_ACCESS_P_NA_U_X
User mode execution only.
Definition: mpu.h:41
#define XTENSA_MPU_ACCESS_P_RW_U_RWX
Kernel mode read, write.
Definition: mpu.h:59
#define XTENSA_MPU_ACCESS_P_RX_U_NA
Kernel mode read and execution.
Definition: mpu.h:47
static bool xtensa_mem_partition_is_executable(k_mem_partition_attr_t access_rights)
Definition: mpu.h:200
const struct xtensa_mpu_range xtensa_soc_mpu_ranges[]
Additional memory regions required by SoC.
#define XTENSA_MPU_ACCESS_P_RX_U_RX
Kernel and user modes read and execution.
Definition: mpu.h:71
#define XTENSA_MPU_NUM_ENTRIES
Number of available entries in the MPU table.
Definition: mpu.h:24
#define XTENSA_MPU_ACCESS_P_RWX_U_NA
Kernel mode read, write and execution.
Definition: mpu.h:53
#define XTENSA_MPU_ACCESS_P_X_U_NA
Kernel mode execution only.
Definition: mpu.h:38
__UINT32_TYPE__ uint32_t
Definition: stdint.h:90
__UINT8_TYPE__ uint8_t
Definition: stdint.h:88
__UINTPTR_TYPE__ uintptr_t
Definition: stdint.h:105
__UINT16_TYPE__ uint16_t
Definition: stdint.h:89
Definition: arm_mpu_v7m.h:160
Foreground MPU Entry.
Definition: mpu.h:89
uint32_t mbz1
Must be zero (part 1).
Definition: mpu.h:151
uint32_t mbz
Must be zero.
Definition: mpu.h:124
uint32_t memory_type
Memory type associated with this MPU entry.
Definition: mpu.h:175
uint32_t segment
The segment number of this MPU entry.
Definition: mpu.h:148
struct xtensa_mpu_entry::@36::@38 p
Individual parts.
uint32_t raw
Raw value.
Definition: mpu.h:97
uint32_t lock
Lock bit for this entry.
Definition: mpu.h:121
uint32_t access_rights
Access rights associated with this MPU entry.
Definition: mpu.h:161
union xtensa_mpu_entry::@37 at
Content of at register for WPTLB.
uint32_t start_addr
Start address of this MPU entry.
Definition: mpu.h:132
union xtensa_mpu_entry::@36 as
Content of as register for WPTLB.
uint32_t enable
Enable bit for this entry.
Definition: mpu.h:107
uint32_t mbz2
Must be zero (part 2).
Definition: mpu.h:178
Struct to hold foreground MPU map and its entries.
Definition: mpu.h:186
struct xtensa_mpu_entry entries[XCHAL_MPU_ENTRIES]
Array of MPU entries.
Definition: mpu.h:190
Struct to describe a memory region [start, end).
Definition: mpu.h:275
const uint8_t access_rights
Access rights for the memory region.
Definition: mpu.h:287
const uintptr_t start
Start address (inclusive) of the memory region.
Definition: mpu.h:277
const uintptr_t end
End address (exclusive) of the memory region.
Definition: mpu.h:284
const uint16_t memory_type
Memory type for the region.
Definition: mpu.h:296
Macros to abstract toolchain specific capabilities.
Macro utilities.