Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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stm32u5_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 * Copyright (c) 2023 STMicroelectronics
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
9
10#include "stm32_common_clocks.h"
11
14/* RM0468, Table 56 Kernel clock distribution summary */
15
17/* defined in stm32_common_clocks.h */
19#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
20#define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)
21#define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1)
22#define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1)
23#define STM32_SRC_MSIK (STM32_SRC_MSIS + 1)
25#define STM32_SRC_PLL1_P (STM32_SRC_MSIK + 1)
26#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
27#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
28#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
29#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
30#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
31#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
32#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
33#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
35/* #define STM32_SRC_ICLK TBD */
36
38#define STM32_CLOCK_BUS_AHB1 0x088
39#define STM32_CLOCK_BUS_AHB2 0x08C
40#define STM32_CLOCK_BUS_AHB2_2 0x090
41#define STM32_CLOCK_BUS_AHB3 0x094
42#define STM32_CLOCK_BUS_APB1 0x09C
43#define STM32_CLOCK_BUS_APB1_2 0x0A0
44#define STM32_CLOCK_BUS_APB2 0x0A4
45#define STM32_CLOCK_BUS_APB3 0x0A8
46
47#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
48#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
49
50#define STM32_CLOCK_REG_MASK 0xFFU
51#define STM32_CLOCK_REG_SHIFT 0U
52#define STM32_CLOCK_SHIFT_MASK 0x1FU
53#define STM32_CLOCK_SHIFT_SHIFT 8U
54#define STM32_CLOCK_MASK_MASK 0x7U
55#define STM32_CLOCK_MASK_SHIFT 13U
56#define STM32_CLOCK_VAL_MASK 0x7U
57#define STM32_CLOCK_VAL_SHIFT 16U
58
72#define STM32_CLOCK(val, mask, shift, reg) \
73 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
74 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
75 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
76 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
77
79#define CCIPR1_REG 0xE0
80#define CCIPR2_REG 0xE4
81#define CCIPR3_REG 0xE8
82
84#define BDCR_REG 0xF0
85
88#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG)
89#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG)
90#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR1_REG)
91#define UART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR1_REG)
92#define UART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR1_REG)
93#define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG)
94#define I2C2_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR1_REG)
95#define I2C4_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR1_REG)
96#define SPI2_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR1_REG)
97#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR1_REG)
98#define SPI1_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR1_REG)
99#define SYSTICK_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR1_REG)
100#define FDCAN1_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR1_REG)
101#define ICKLK_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR1_REG)
102#define TIMIC_SEL(val) STM32_CLOCK(val, 7, 29, CCIPR1_REG)
104#define MDF1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR2_REG)
105#define SAI1_SEL(val) STM32_CLOCK(val, 7, 5, CCIPR2_REG)
106#define SAI2_SEL(val) STM32_CLOCK(val, 7, 8, CCIPR2_REG)
107#define SAE_SEL(val) STM32_CLOCK(val, 1, 11, CCIPR2_REG)
108#define RNG_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG)
109#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG)
110#define DSIHOST_SEL(val) STM32_CLOCK(val, 1, 15, CCIPR2_REG)
111#define USART6_SEL(val) STM32_CLOCK(val, 1, 16, CCIPR2_REG)
112#define LTDC_SEL(val) STM32_CLOCK(val, 1, 18, CCIPR2_REG)
113#define OCTOSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG)
114#define HSPI_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR2_REG)
115#define I2C5_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR2_REG)
116#define I2C6_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR2_REG)
117#define USBPHYC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR2_REG)
119#define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR3_REG)
120#define SPI3_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR3_REG)
121#define I2C3_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR3_REG)
122#define LPTIM34_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR3_REG)
123#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR3_REG)
124#define ADCDAC_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR3_REG)
125#define DAC1_SEL(val) STM32_CLOCK(val, 1, 15, CCIPR3_REG)
126#define ADF1_SEL(val) STM32_CLOCK(val, 7, 16, CCIPR3_REG)
128#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG)
129
130#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */