Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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stm32mp1_reset.h
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1/*
2 * Copyright (c) 2022 Google Inc
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP1_RESET_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP1_RESET_H_
9
20#define STM32_RESET(bus, bit) \
21 (((STM32_RESET_BUS_##bus##_CLR) << 17U) | ((STM32_RESET_BUS_##bus##_SET) << 5U) | (bit))
22
23/* RCC bus reset register offset */
24#define STM32_RESET_BUS_AHB2_SET 0x998
25#define STM32_RESET_BUS_AHB2_CLR 0x99C
26#define STM32_RESET_BUS_AHB3_SET 0x9A0
27#define STM32_RESET_BUS_AHB3_CLR 0x9A4
28#define STM32_RESET_BUS_AHB4_SET 0x9A8
29#define STM32_RESET_BUS_AHB4_CLR 0x9AC
30#define STM32_RESET_BUS_AHB5_SET 0x190
31#define STM32_RESET_BUS_AHB5_CLR 0x194
32#define STM32_RESET_BUS_AHB6_SET 0x198
33#define STM32_RESET_BUS_AHB6_CLR 0x19C
34#define STM32_RESET_BUS_TZAHB6_SET 0x1A0
35#define STM32_RESET_BUS_TZAHB6_CLR 0x1A4
36#define STM32_RESET_BUS_APB1_SET 0x980
37#define STM32_RESET_BUS_APB1_CLR 0x984
38#define STM32_RESET_BUS_APB2_SET 0x988
39#define STM32_RESET_BUS_APB2_CLR 0x98C
40#define STM32_RESET_BUS_APB3_SET 0x990
41#define STM32_RESET_BUS_APB3_CLR 0x994
42#define STM32_RESET_BUS_APB4_SET 0x180
43#define STM32_RESET_BUS_APB4_CLR 0x184
44#define STM32_RESET_BUS_APB5_SET 0x188
45#define STM32_RESET_BUS_APB5_CLR 0x18C
46
47#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP1_RESET_H_ */