Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
stm32l0_clock.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
8
10
12#define STM32_CLOCK_BUS_IOP 0x02c
13#define STM32_CLOCK_BUS_AHB1 0x030
14#define STM32_CLOCK_BUS_APB2 0x034
15#define STM32_CLOCK_BUS_APB1 0x038
16
17#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
18#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
19
21/* RM0367, ยง7.3.20 Clock configuration register (RCC_CCIPR) */
22
24/* defined in stm32_common_clocks.h */
25
27/* Low speed clocks defined in stm32_common_clocks.h */
28#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
29#define STM32_SRC_HSI (STM32_SRC_HSE + 1)
30#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
32#define STM32_SRC_PCLK (STM32_SRC_HSI48 + 1)
33
34#define STM32_CLOCK_REG_MASK 0xFFU
35#define STM32_CLOCK_REG_SHIFT 0U
36#define STM32_CLOCK_SHIFT_MASK 0x1FU
37#define STM32_CLOCK_SHIFT_SHIFT 8U
38#define STM32_CLOCK_MASK_MASK 0x7U
39#define STM32_CLOCK_MASK_SHIFT 13U
40#define STM32_CLOCK_VAL_MASK 0x7U
41#define STM32_CLOCK_VAL_SHIFT 16U
42
56#define STM32_CLOCK(val, mask, shift, reg) \
57 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
58 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
59 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
60 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
61
63#define CCIPR_REG 0x4C
64
66#define CSR_REG 0x50
67
70#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
71#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
72#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
73#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
74#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
75#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
76#define HSI48_SEL(val) STM32_CLOCK(val, 1, 26, CCIPR_REG)
78#define RTC_SEL(val) STM32_CLOCK(val, 3, 16, CSR_REG)
79
80#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */