Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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npcx7_reset.h
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1/*
2 * Copyright (c) 2024 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H
8#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H
9
10#define NPCX_RESET_SWRST_CTL1_OFFSET 0
11#define NPCX_RESET_SWRST_CTL2_OFFSET 32
12#define NPCX_RESET_SWRST_CTL3_OFFSET 64
13
14#define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0)
15#define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1)
16#define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2)
17#define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3)
18#define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4)
19#define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5)
20#define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6)
21#define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7)
22#define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8)
23#define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9)
24#define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10)
25#define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11)
26#define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12)
27#define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13)
28#define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14)
29#define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15)
30#define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16)
31#define NPCX_RESET_ITIM16_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18)
32#define NPCX_RESET_ITIM16_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19)
33#define NPCX_RESET_ITIM16_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20)
34#define NPCX_RESET_ITIM16_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21)
35#define NPCX_RESET_ITIM16_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22)
36#define NPCX_RESET_ITIM16_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23)
37#define NPCX_RESET_ITIM32 (NPCX_RESET_SWRST_CTL1_OFFSET + 24)
38#define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25)
39#define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26)
40#define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27)
41#define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28)
42#define NPCX_RESET_GDMA (NPCX_RESET_SWRST_CTL1_OFFSET + 29)
43#define NPCX_RESET_FIU (NPCX_RESET_SWRST_CTL1_OFFSET + 30)
44
45#define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0)
46#define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2)
47#define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3)
48#define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5)
49#define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6)
50#define NPCX_RESET_ADC (NPCX_RESET_SWRST_CTL2_OFFSET + 7)
51#define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8)
52#define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9)
53#define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10)
54#define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11)
55#define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12)
56#define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13)
57#define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14)
58#define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15)
59#define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16)
60#define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17)
61#define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18)
62#define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19)
63#define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20)
64#define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21)
65#define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22)
66#define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23)
67#define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24)
68#define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25)
69#define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26)
70#define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27)
71#define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28)
72#define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29)
73#define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30)
74#define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31)
75
76#define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0)
77#define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1)
78#define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8)
79#define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9)
80#define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10)
81#define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11)
82#define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12)
83#define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13)
84#define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15)
85#define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16)
86#define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20)
87#define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22)
88#define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23)
89#define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24)
90#define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25)
91
92#define NPCX_RESET_ID_START NPCX_RESET_GPIO0
93#define NPCX_RESET_ID_END NPCX_RESET_BBRAM
94#endif