Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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memory-attr-riscv.h
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1/*
2 * Copyright (c) 2023 Carlo Caione <[email protected]>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_RISCV_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_RISCV_H_
8
11
12/*
13 * Architecture specific RISCV related attributes.
14 */
15#define DT_MEM_RISCV_MASK DT_MEM_ARCH_ATTR_MASK
16#define DT_MEM_RISCV_GET(x) ((x) & DT_MEM_RISCV_MASK)
17#define DT_MEM_RISCV(x) ((x) << DT_MEM_ARCH_ATTR_SHIFT)
18
19#define ATTR_RISCV_TYPE_MAIN BIT(0)
20#define ATTR_RISCV_TYPE_IO BIT(1)
21#define ATTR_RISCV_TYPE_EMPTY BIT(2)
22#define ATTR_RISCV_AMO_SWAP BIT(3)
23#define ATTR_RISCV_AMO_LOGICAL BIT(4)
24#define ATTR_RISCV_AMO_ARITHMETIC BIT(5)
25#define ATTR_RISCV_IO_IDEMPOTENT_READ BIT(6)
26#define ATTR_RISCV_IO_IDEMPOTENT_WRITE BIT(7)
27
28#define DT_MEM_RISCV_TYPE_MAIN DT_MEM_RISCV(ATTR_RISCV_TYPE_MAIN)
29#define DT_MEM_RISCV_TYPE_IO DT_MEM_RISCV(ATTR_RISCV_TYPE_IO)
30#define DT_MEM_RISCV_TYPE_EMPTY DT_MEM_RISCV(ATTR_RISCV_TYPE_EMPTY)
31#define DT_MEM_RISCV_AMO_SWAP DT_MEM_RISCV(ATTR_RISCV_AMO_SWAP)
32#define DT_MEM_RISCV_AMO_LOGICAL DT_MEM_RISCV(ATTR_RISCV_AMO_LOGICAL)
33#define DT_MEM_RISCV_AMO_ARITHMETIC DT_MEM_RISCV(ATTR_RISCV_AMO_ARITHMETIC)
34#define DT_MEM_RISCV_IO_IDEMPOTENT_READ DT_MEM_RISCV(ATTR_RISCV_IO_IDEMPOTENT_READ)
35#define DT_MEM_RISCV_IO_IDEMPOTENT_WRITE DT_MEM_RISCV(ATTR_RISCV_IO_IDEMPOTENT_WRITE)
36#define DT_MEM_RISCV_UNKNOWN DT_MEM_ARCH_ATTR_UNKNOWN
37
38#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_RISCV_H_ */
Macro utilities.