Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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irq_multilevel.h
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1/*
2 * Copyright (c) 2023 Meta
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
11#ifndef ZEPHYR_INCLUDE_IRQ_MULTILEVEL_H_
12#define ZEPHYR_INCLUDE_IRQ_MULTILEVEL_H_
13
14#ifndef _ASMLANGUAGE
16#include <zephyr/types.h>
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#if defined(CONFIG_MULTI_LEVEL_INTERRUPTS) || defined(__DOXYGEN__)
31static inline unsigned int irq_get_level(unsigned int irq)
32{
33 const uint32_t mask2 = BIT_MASK(CONFIG_2ND_LEVEL_INTERRUPT_BITS) <<
34 CONFIG_1ST_LEVEL_INTERRUPT_BITS;
35 const uint32_t mask3 = BIT_MASK(CONFIG_3RD_LEVEL_INTERRUPT_BITS) <<
36 (CONFIG_1ST_LEVEL_INTERRUPT_BITS + CONFIG_2ND_LEVEL_INTERRUPT_BITS);
37
38 if (IS_ENABLED(CONFIG_3RD_LEVEL_INTERRUPTS) && (irq & mask3) != 0) {
39 return 3;
40 }
41
42 if (IS_ENABLED(CONFIG_2ND_LEVEL_INTERRUPTS) && (irq & mask2) != 0) {
43 return 2;
44 }
45
46 return 1;
47}
48
59static inline unsigned int irq_from_level_2(unsigned int irq)
60{
61 if (IS_ENABLED(CONFIG_3RD_LEVEL_INTERRUPTS)) {
62 return ((irq >> CONFIG_1ST_LEVEL_INTERRUPT_BITS) &
63 BIT_MASK(CONFIG_2ND_LEVEL_INTERRUPT_BITS)) - 1;
64 } else {
65 return (irq >> CONFIG_1ST_LEVEL_INTERRUPT_BITS) - 1;
66 }
67}
68
76#define IRQ_TO_L2(irq) ((irq + 1) << CONFIG_1ST_LEVEL_INTERRUPT_BITS)
77
90static inline unsigned int irq_to_level_2(unsigned int irq)
91{
92 return IRQ_TO_L2(irq);
93}
94
105static inline unsigned int irq_parent_level_2(unsigned int irq)
106{
107 return irq & BIT_MASK(CONFIG_1ST_LEVEL_INTERRUPT_BITS);
108}
109
121static inline unsigned int irq_from_level_3(unsigned int irq)
122{
123 return (irq >> (CONFIG_1ST_LEVEL_INTERRUPT_BITS + CONFIG_2ND_LEVEL_INTERRUPT_BITS)) - 1;
124}
125
133#define IRQ_TO_L3(irq) \
134 ((irq + 1) << (CONFIG_1ST_LEVEL_INTERRUPT_BITS + CONFIG_2ND_LEVEL_INTERRUPT_BITS))
135
148static inline unsigned int irq_to_level_3(unsigned int irq)
149{
150 return IRQ_TO_L3(irq);
151}
152
163static inline unsigned int irq_parent_level_3(unsigned int irq)
164{
165 return (irq >> CONFIG_1ST_LEVEL_INTERRUPT_BITS) &
166 BIT_MASK(CONFIG_2ND_LEVEL_INTERRUPT_BITS);
167}
168
169#endif /* CONFIG_MULTI_LEVEL_INTERRUPTS */
170#ifdef __cplusplus
171}
172#endif
173
174#endif /* _ASMLANGUAGE */
175#endif /* ZEPHYR_INCLUDE_IRQ_MULTILEVEL_H_ */
#define IS_ENABLED(config_macro)
Check for macro definition in compiler-visible expressions.
Definition: util_macro.h:124
#define BIT_MASK(n)
Bit mask with bits 0 through n-1 (inclusive) set, or 0 if n is 0.
Definition: util_macro.h:68
#define IRQ_TO_L3(irq)
Preprocessor macro to convert irq from level 1 to level 3 format.
Definition: irq_multilevel.h:133
static unsigned int irq_to_level_3(unsigned int irq)
Converts irq from level 1 to level 3 format.
Definition: irq_multilevel.h:148
static unsigned int irq_from_level_3(unsigned int irq)
Return the 3rd level interrupt number.
Definition: irq_multilevel.h:121
static unsigned int irq_from_level_2(unsigned int irq)
Return the 2nd level interrupt number.
Definition: irq_multilevel.h:59
static unsigned int irq_get_level(unsigned int irq)
Return IRQ level This routine returns the interrupt level number of the provided interrupt.
Definition: irq_multilevel.h:31
static unsigned int irq_to_level_2(unsigned int irq)
Converts irq from level 1 to level 2 format.
Definition: irq_multilevel.h:90
#define IRQ_TO_L2(irq)
Preprocessor macro to convert irq from level 1 to level 2 format.
Definition: irq_multilevel.h:76
static unsigned int irq_parent_level_2(unsigned int irq)
Returns the parent IRQ of the level 2 raw IRQ number.
Definition: irq_multilevel.h:105
static unsigned int irq_parent_level_3(unsigned int irq)
Returns the parent IRQ of the level 3 raw IRQ number.
Definition: irq_multilevel.h:163
__UINT32_TYPE__ uint32_t
Definition: stdint.h:90
Macro utilities.