Zephyr API 3.6.99
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dma_mcux_lpc.h
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1/*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_DMA_MCUX_LPC_H_
8#define ZEPHYR_INCLUDE_DRIVERS_DMA_DMA_MCUX_LPC_H_
9
10/*
11 * LPC DMA engine channel hardware trigger attributes.
12 * These attributes can be set to the "dma_slot" field
13 * in a dma_config structure to configure a channel for
14 * hardware triggering.
15 */
16
17/* Peripheral request enable. When set, the peripheral
18 * request line associated with this channel is used to pace DMA transfers.
19 */
20#define LPC_DMA_PERIPH_REQ_EN BIT(0)
21
22/* Hardware trigger enable. When set, the hardware trigger connected to this
23 * channel via INPUTMUX can be used to trigger a transfer
24 */
25#define LPC_DMA_HWTRIG_EN BIT(1)
26
27/* HW trigger polarity. When this bit is set, the trigger will be active
28 * high or rising edge triggered, based on TRIG_TYPE selection
29 */
30#define LPC_DMA_TRIGPOL_HIGH_RISING BIT(2)
31
32/* HW trigger type. When this bit is set, the trigger will be level triggered.
33 * When it is cleared, the hardware trigger will be edge triggered.
34 */
35#define LPC_DMA_TRIGTYPE_LEVEL BIT(3)
36
37/* HW trigger burst mode. When set, the hardware trigger will cause a burst
38 * transfer to occur, the length of which is determined by BURST_POWER.
39 * When cleared, a single transfer (of the width selected by XFERCFG register)
40 * will occur.
41 */
42#define LPC_DMA_TRIGBURST BIT(4)
43
44/* HW trigger burst power. Note that due to the size limit of the dma_slot
45 * field, the maximum transfer burst possible is 128. The hardware supports
46 * up to 1024 transfers in BURSTPOWER. The value set here will result in
47 * 2^BURSTPOWER transfers occurring. So for BURSTPOWER=3, 8 transfers would
48 * occur.
49 */
50#define LPC_DMA_BURSTPOWER(pwr) (((pwr) & 0x7) << 5)
51
52
53/* Used by driver to extract burstpower setting */
54#define LPC_DMA_GET_BURSTPOWER(slot) (((slot) & 0xE0) >> 5)
55
56#endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_DMA_MCUX_LPC_H_ */