Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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thread.h
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1/*
2 * Copyright (c) 2017 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
19#ifndef ZEPHYR_INCLUDE_ARCH_ARM_THREAD_H_
20#define ZEPHYR_INCLUDE_ARCH_ARM_THREAD_H_
21
22#ifndef _ASMLANGUAGE
23#include <zephyr/types.h>
24
25struct _callee_saved {
26 uint32_t v1; /* r4 */
27 uint32_t v2; /* r5 */
28 uint32_t v3; /* r6 */
29 uint32_t v4; /* r7 */
30 uint32_t v5; /* r8 */
31 uint32_t v6; /* r9 */
32 uint32_t v7; /* r10 */
33 uint32_t v8; /* r11 */
34 uint32_t psp; /* r13 */
35#ifdef CONFIG_USE_SWITCH
36 uint32_t lr; /* lr */
37#endif
38};
39
40typedef struct _callee_saved _callee_saved_t;
41
42#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
43struct _preempt_float {
44 float s16;
45 float s17;
46 float s18;
47 float s19;
48 float s20;
49 float s21;
50 float s22;
51 float s23;
52 float s24;
53 float s25;
54 float s26;
55 float s27;
56 float s28;
57 float s29;
58 float s30;
59 float s31;
60};
61#endif
62
63struct _thread_arch {
64
65 /* interrupt locking key */
66 uint32_t basepri;
67
68 /* r0 in stack frame cannot be written to reliably */
69 uint32_t swap_return_value;
70
71#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
72 /*
73 * No cooperative floating point register set structure exists for
74 * the Cortex-M as it automatically saves the necessary registers
75 * in its exception stack frame.
76 */
77 struct _preempt_float preempt_float;
78#endif
79
80#if defined(CONFIG_CPU_AARCH32_CORTEX_A) || defined(CONFIG_CPU_AARCH32_CORTEX_R)
81 int8_t exception_depth;
82#endif
83
84#if defined(CONFIG_ARM_STORE_EXC_RETURN) || defined(CONFIG_USERSPACE)
85 /*
86 * Status variable holding several thread status flags
87 * as follows:
88 *
89 * byte 0
90 * +-bits 4-7-----bit-3----------bit-2--------bit-1---+----bit-0------+
91 * : | | | | |
92 * : reserved |<Guard FLOAT>| reserved | reserved | <priv mode> |
93 * : bits | | | | CONTROL.nPRIV |
94 * +------------------------------------------------------------------+
95 *
96 * byte 1
97 * +----------------------------bits 8-15-----------------------------+
98 * : Least significant byte of EXC_RETURN |
99 * : bit 15| bit 14| bit 13 | bit 12| bit 11 | bit 10 | bit 9 | bit 8 |
100 * : Res | S | DCRS | FType | Mode | SPSel | Res | ES |
101 * +------------------------------------------------------------------+
102 *
103 * Bit 0: thread's current privileged mode (Supervisor or User mode)
104 * Mirrors CONTROL.nPRIV flag.
105 * Bit 2: Deprecated in favor of FType. Note: FType = !CONTROL.FPCA.
106 * indicating whether the thread has an active FP context.
107 * Mirrors CONTROL.FPCA flag.
108 * Bit 3: indicating whether the thread is applying the long (FLOAT)
109 * or the default MPU stack guard size.
110 *
111 * Bits 8-15: Least significant octet of the EXC_RETURN value when a
112 * thread is switched-out. The value is copied from LR when
113 * entering the PendSV handler. When the thread is
114 * switched in again, the value is restored to LR before
115 * exiting the PendSV handler.
116 */
117 union {
118 uint32_t mode;
119
120#if defined(CONFIG_ARM_STORE_EXC_RETURN)
121 struct {
122 uint8_t mode_bits;
123 uint8_t mode_exc_return;
124 uint16_t mode_reserved2;
125 };
126#endif
127 };
128
129#if defined(CONFIG_USERSPACE)
130 uint32_t priv_stack_start;
131#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
132 uint32_t priv_stack_end;
133 uint32_t sp_usr;
134#endif
135#endif
136#endif
137};
138
139#if defined(CONFIG_FPU_SHARING) && defined(CONFIG_MPU_STACK_GUARD)
140#define Z_ARM_MODE_MPU_GUARD_FLOAT_Msk (1 << 3)
141#endif
142typedef struct _thread_arch _thread_arch_t;
143
144#endif /* _ASMLANGUAGE */
145
146#endif /* ZEPHYR_INCLUDE_ARCH_ARM_THREAD_H_ */
__UINT32_TYPE__ uint32_t
Definition: stdint.h:90
__UINT8_TYPE__ uint8_t
Definition: stdint.h:88
__UINT16_TYPE__ uint16_t
Definition: stdint.h:89
__INT8_TYPE__ int8_t
Definition: stdint.h:72