xlnx,xps-spi-2.00.a

Vendor: Xilinx

Description

These nodes are “spi” bus nodes.

Xilinx AXI Quad SPI IP node

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-frequency

int

 
Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

 
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

overrun-character

int

 
The overrun character (ORC) is used when all bytes from the TX buffer
are sent, but the transfer continues due to RX.

xlnx,num-ss-bits

int

 
Number of slave select bits implemented

This property is required.

Legal values: 1, 2, 3, 4

xlnx,num-transfer-bits

int

 
Number of bits per transfer

This property is required.

Legal values: 8, 16, 32

xlnx,startup-block

boolean

 
Indicates the core is instantiated with the STARTUP block option, as is
typically used when interfacing with the FPGA's configuration flash
device. In this configuration the SPI clock is routed through the
STARTUP block rather than normal signal routing.
In this case, a workaround is required to issue a dummy
transaction to the SPI flash device to ensure the STARTUP block is
disengaged and allow the SPI core to control the CCLK line properly.
The dummy READ_ID transaction will be issued to chip select 0.

fifo-size

int

 
FIFO size configured in SPI core. 0 indicates no FIFO.
If not specified, 0 is assumed.
Used to optimize TX/RX read handling. If the FIFO size is 0, the driver
will check for FIFO full/empty after every word.