renesas,smartbond-nor-psram

Vendor: Renesas Electronics Corporation

Description

Renesas Smartbond(tm) NOR/PSRAM controller

Properties

Properties not inherited from the base binding file.

Name

Type

Details

is-ram

boolean

If present, the memory controller will be configured to drive PSRAM devices.

dev-size

int

Memory size/capacity in bits.

This property is required.

dev-type

int

Device type, part of device ID, used to verify the memory device used.

This property is required.

dev-density

int

Device density, part of device ID, used to verify the memory device used.
[7:0] should reflect the density value itself and [15:8] should reflect
the mask that should be applied to the returned device ID value.
This is because part of its byte value might contain invalid bits.

This property is required.

dev-id

int

Manufacturer ID, part of device ID, used to verify the memory device used.

This property is required.

reset-delay-us

int

Time in microseconds (us) the memory device can accept the next command following a SW reset.

This property is required.

read-cs-idle-min-ns

int

Min. time, in nanoseconds, the #CS line should remain inactive between
the transmission of two different instructions.

This property is required.

erase-cs-idle-min-ns

int

Min. time, in nanoseconds, the #CS line should remain inactive after the execution
of a write enable, erase, erase suspend or erase resume instruction. This setting
is not used if is-ram property is present.

enter-qpi-cmd

int

Command to enter the QPI mode supported by a memory device
(should be transmitted in single bus mode).

exit-qpi-cmd

int

Command to exit the QPI mode supported by a memory device
(should be transmitted in quad bus mode).

enter-qpi-mode

boolean

If present, the memory device will enter the QPI mode which typically reflects that
all bytes be sent in quad bus mode. It's a pre-requisite that read and write
commands, that should be read-cmd and write-cmd respectively, reflect the QPI mode.

read-cmd

int

Read command for single/burst read accesses in auto mode. Default value is the opcode
for single mode which is supported by all memory devices.

Default value: 3

write-cmd

int

Write command for single/burst write accesses in auto mode. Default value is the opcode
for single mode which is supported by all memory devices.

Default value: 2

clock-mode

string

Clock mode when #CS is idle/inactive

- Mode0: #CLK is low when #CS is inactive
- Mode3: #CLK is high when #CS is inactive

Mode0 is selected by default as it should be supported by all memory devices.

Default value: spi-mode0

Legal values: 'spi-mode0', 'spi-mode3'

addr-range

string

Address size to use in auto mode. In 24-bit mode up to 16MB can be
accessed whilst in 32-bit mode up to 32MB can be accessed which is
the max. address space supported by QSPICx. Default value is 24-bit
mode which is supported by all memory devices.

Default value: addr-range-24bit

Legal values: 'addr-range-24bit', 'addr-range-32bit'

clock-div

int

Clock divider for QSPIC2 controller. The clock path of
this block is always DIV1 which reflects the current
system clock.

tcem-max-us

int

If a non zero value is applied, then Tcem should be taken into
consideration by QSPIC2 so that it can split a burst read/write
access in case the total time exceeds the defined value
(at the cost of extra cycles required for re-sending the instruction,
address and dummy bytes, if any). This setting is meaningful only if
is-ram is present. This value reflects the max. time in microseconds
the #CS line can be driven low in a write/read burst access
(required for the auto-refresh mechanism, when supported).

dummy-bytes-count

string

Number of dummy bytes to send for single/burst read access in auto mode.

This property is required.

Legal values: 'dummy-bytes-count0', 'dummy-bytes-count1', 'dummy-bytes-count2', 'dummy-bytes-count4'

extra-byte-enable

boolean

If present, the extra byte will be sent after the dummy bytes, if any.
This should be useful if 3 dummy bytes are required. In such a case,
dummy-bytes-count should be set to 2.

extra-byte

int

Extra byte to be sent, if extra-byte-enable is present.

rx-addr-mode

string

Describes the mode of SPI bus during the address phase for single/burst
read accesses in auto mode. Default value is single mode which should be
supported by all memory devices.

Default value: single-spi

Legal values: 'single-spi', 'dual-spi', 'quad-spi'

rx-inst-mode

string

Describes the mode of SPI bus during the instruction phase for single/burst
read accesses in auto mode. Default value is single mode which should be
supported by all memory devices.

Default value: single-spi

Legal values: 'single-spi', 'dual-spi', 'quad-spi'

rx-data-mode

string

Describes the mode of SPI bus during the data phase for single/burst
read accesses in auto mode. Default value is single mode which should
be supported by all memory devices.

Default value: single-spi

Legal values: 'single-spi', 'dual-spi', 'quad-spi'

rx-dummy-mode

string

Describes the mode of SPI bus during the dummy bytes phase for single/burst
read accesses in auto mode. The single mode should be supported by all
memory devices.

Default value: single-spi

Legal values: 'single-spi', 'dual-spi', 'quad-spi'

rx-extra-mode

string

Describes the mode of SPI bus during the extra byte phase for single/burst
read accesses in auto mode. Default value is single mode which should be
supported by all memory devices.

Legal values: 'single-spi', 'dual-spi', 'quad-spi'

tx-addr-mode

string

Describes the mode of SPI bus during the address phase for single/burst
write accesses in auto mode. Default value is single mode which should
be supported by all memory devices.

Default value: single-spi

Legal values: 'single-spi', 'dual-spi', 'quad-spi'

tx-inst-mode

string

Describes the mode of SPI bus during the instruction phase for single/burst
write accesses in auto mode. The single mode should be supported by all
memory devices.

Default value: single-spi

Legal values: 'single-spi', 'dual-spi', 'quad-spi'

tx-data-mode

string

Describes the mode of SPI bus during the data phase for single/burst
write accesses in auto mode. Default value is single mode which should
be supported by all memory devices.

Default value: single-spi

Legal values: 'single-spi', 'dual-spi', 'quad-spi'