lattice,ice40-fpga (on spi bus)

Vendor: Lattice Semiconductor

Description

Lattice iCE40 FPGA

Properties

Properties not inherited from the base binding file.

Name

Type

Details

supply-gpios

phandle-array

 
GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.

vin-supply

phandle

 
Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.

spi-max-frequency

int

 
Maximum clock frequency of device's SPI interface in Hz

This property is required.

duplex

int

 
Duplex mode, full or half. By default it's always full duplex thus 0
as this is, by far, the most common mode.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0    SPI_FULL_DUPLEX
  2048 SPI_HALF_DUPLEX

Legal values: 0, 2048

frame-format

int

 
Motorola or TI frame format. By default it's always Motorola's,
thus 0 as this is, by far, the most common format.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0     SPI_FRAME_FORMAT_MOTOROLA
  32768 SPI_FRAME_FORMAT_TI

Legal values: 0, 32768

spi-cpol

boolean

 
SPI clock polarity which indicates the clock idle state.
If it is used, the clock idle state is logic high; otherwise, low.

spi-cpha

boolean

 
SPI clock phase that indicates on which edge data is sampled.
If it is used, data is sampled on the second edge; otherwise, on the first edge.

spi-hold-cs

boolean

 
In some cases, it is necessary for the master to manage SPI chip select
under software control, so that multiple spi transactions can be performed
without releasing it. A typical use case is variable length SPI packets
where the first spi transaction reads the length and the second spi transaction
reads length bytes.

load-mode

int

 
Configure the method used to load the bitstream.
The bitstream may be loaded via 2 separate methods:
0 := load the FPGA via SPI transfer
1 := load the FPGA via bit-banged GPIO
Option 0 may be suitable for some high-end microcontrollers.
Option 1 is suitable for low-end microcontrollers. This option
requires clk-gpios, pico-gpios, gpios-set-reg, and gpios-clear-reg
to be defined.
Example usage:
load-mode = <0>;

This property is required.

cdone-gpios

phandle-array

 
Configuration Done output from iCE40.
Example usage:
cdone-gpios = <&gpio0 0 0>;

This property is required.

creset-gpios

phandle-array

 
Configuration Reset input on iCE40.
Example usage:
creset-gpios = <&gpio0 1 GPIO_PUSH_PULL);

This property is required.

clk-gpios

phandle-array

 
SPI Clock GPIO input on iCE40.
Example usage:
clk-gpios = <&gpio0 5 GPIO_PUSH_PULL>;

pico-gpios

phandle-array

 
Peripheral-In Controller-Out GPIO input on iCE40.
Example usage:
pico-gpios = <&gpio0 7 GPIO_PUSH_PULL>;

gpios-set-reg

int

 
Register address for setting a GPIO.
Example usage:
gpios-set-reg = <0x60004008>;

gpios-clear-reg

int

 
Register address for clearing a GPIO.
Example usage:
gpios-clear-reg = <0x6000400c>;

mhz-delay-count

int

 
in order to create a 1 MHz square wave in the following
process.
while(true) {
  *gpios_set_reg |= BIT(n);
  for(int i = mhz_delay_count; i > 0; --i);
  *gpios_clear_reg |= BIT(n);
  for(int i = mhz_delay_count; i > 0; --i);
}
Example usage / default:
mhz-delay-count = <0>;

creset-delay-us

int

 
Delay (in microseconds) between asserting CRESET_B and releasing CRESET_B.
Example usage / default:
creset-delay-us = <1>;

config-delay-us

int

 
Delay (in microseconds) after releasing CRESET_B to clear internal configuration memory.
Example usage / default:
config-delay-us = <1200>;

leading-clocks

int

 
Prior to sending the bitstream, issue this number of leading clocks with SPI_CS pulled high.
Example usage / default:
leading-clocks = <8>;

trailing-clocks

int

 
After sending the bitstream, issue this number of trailing clocks with SPI_CS pulled high.
Example usage / default:
trailing-clocks = <49>;