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memory_map.h
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MEMORY_MAP_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MEMORY_MAP_H_
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#include <
zephyr/sys/util.h
>
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/* 0x00000000 -> 0x1fffffff: Code in ROM [0.5 GB] */
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#define _CODE_BASE_ADDR 0x00000000
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#define _CODE_END_ADDR 0x1FFFFFFF
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/* 0x20000000 -> 0x3fffffff: SRAM [0.5GB] */
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#define _SRAM_BASE_ADDR 0x20000000
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#define _SRAM_BIT_BAND_REGION 0x20000000
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#define _SRAM_BIT_BAND_REGION_END 0x200FFFFF
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#define _SRAM_BIT_BAND_ALIAS 0x22000000
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#define _SRAM_BIT_BAND_ALIAS_END 0x23FFFFFF
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#define _SRAM_END_ADDR 0x3FFFFFFF
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/* 0x40000000 -> 0x5fffffff: Peripherals [0.5GB] */
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#define _PERI_BASE_ADDR 0x40000000
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#define _PERI_BIT_BAND_REGION 0x40000000
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#define _PERI_BIT_BAND_REGION_END 0x400FFFFF
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#define _PERI_BIT_BAND_ALIAS 0x42000000
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#define _PERI_BIT_BAND_ALIAS_END 0x43FFFFFF
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#define _PERI_END_ADDR 0x5FFFFFFF
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/* 0x60000000 -> 0x9fffffff: external RAM [1GB] */
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#define _ERAM_BASE_ADDR 0x60000000
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#define _ERAM_END_ADDR 0x9FFFFFFF
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/* 0xa0000000 -> 0xdfffffff: external devices [1GB] */
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#define _EDEV_BASE_ADDR 0xA0000000
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#define _EDEV_END_ADDR 0xDFFFFFFF
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/* 0xe0000000 -> 0xffffffff: varies by processor (see below) */
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/* 0xe0000000 -> 0xe00fffff: private peripheral bus */
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/* 0xe0000000 -> 0xe003ffff: internal [256KB] */
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#define _PPB_INT_BASE_ADDR 0xE0000000
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#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) || \
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defined(CONFIG_CPU_CORTEX_M1)
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#define _PPB_INT_RSVD_0 0xE0000000
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#define _PPB_INT_DWT 0xE0001000
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#define _PPB_INT_BPU 0xE0002000
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#define _PPB_INT_RSVD_1 0xE0003000
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#define _PPB_INT_SCS 0xE000E000
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#define _PPB_INT_RSVD_2 0xE000F000
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#elif defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#define _PPB_INT_ITM 0xE0000000
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#define _PPB_INT_DWT 0xE0001000
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#define _PPB_INT_FPB 0xE0002000
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#define _PPB_INT_RSVD_1 0xE0003000
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#define _PPB_INT_SCS 0xE000E000
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#define _PPB_INT_RSVD_2 0xE000F000
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#elif defined(CONFIG_CPU_CORTEX_M23) || \
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defined(CONFIG_CPU_CORTEX_M33) || \
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defined(CONFIG_CPU_CORTEX_M55)
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#define _PPB_INT_RSVD_0 0xE0000000
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#define _PPB_INT_SCS 0xE000E000
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#define _PPB_INT_SCB 0xE000ED00
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#define _PPB_INT_RSVD_1 0xE002E000
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#else
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#error Unknown CPU
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#endif
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#define _PPB_INT_END_ADDR 0xE003FFFF
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/* 0xe0000000 -> 0xe00fffff: private peripheral bus */
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/* 0xe0040000 -> 0xe00fffff: external [768K] */
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#define _PPB_EXT_BASE_ADDR 0xE0040000
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#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) \
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|| defined(CONFIG_CPU_CORTEX_M1) || defined(CONFIG_CPU_CORTEX_M23)
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#elif defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
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#define _PPB_EXT_TPIU 0xE0040000
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#define _PPB_EXT_ETM 0xE0041000
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#define _PPB_EXT_PPB 0xE0042000
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#define _PPB_EXT_ROM_TABLE 0xE00FF000
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#define _PPB_EXT_END_ADDR 0xE00FFFFF
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#elif defined(CONFIG_CPU_CORTEX_M33) || defined(CONFIG_CPU_CORTEX_M55)
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#undef _PPB_EXT_BASE_ADDR
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#define _PPB_EXT_BASE_ADDR 0xE0044000
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#define _PPB_EXT_ROM_TABLE 0xE00FF000
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#define _PPB_EXT_END_ADDR 0xE00FFFFF
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#elif defined(CONFIG_CPU_CORTEX_M7)
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#define _PPB_EXT_BASE_ADDR 0xE0040000
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#define _PPB_EXT_RSVD_TPIU 0xE0040000
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#define _PPB_EXT_ETM 0xE0041000
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#define _PPB_EXT_CTI 0xE0042000
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#define _PPB_EXT_PPB 0xE0043000
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#define _PPB_EXT_PROC_ROM_TABLE 0xE00FE000
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#define _PPB_EXT_PPB_ROM_TABLE 0xE00FF000
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#else
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#error Unknown CPU
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#endif
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#define _PPB_EXT_END_ADDR 0xE00FFFFF
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/* 0xe0100000 -> 0xffffffff: vendor-specific [0.5GB-1MB or 511MB] */
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#define _VENDOR_BASE_ADDR 0xE0100000
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#define _VENDOR_END_ADDR 0xFFFFFFFF
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#endif
/* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MEMORY_MAP_H_ */
util.h
Misc utilities.
zephyr
arch
arm
cortex_m
memory_map.h
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