xtensa_mmu.h

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/*
 * Copyright (c) 2022 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#include <stdint.h>
 
#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MMU_H
#define ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MMU_H
 
#define XTENSA_MMU_PERM_X               BIT(0)
 
#define XTENSA_MMU_PERM_W               BIT(1)
 
#define XTENSA_MMU_PERM_WX              (XTENSA_MMU_PERM_W | XTENSA_MMU_PERM_X)
 
#define XTENSA_MMU_CACHED_WB            BIT(2)
 
#define XTENSA_MMU_CACHED_WT            BIT(3)
 
typedef uint32_t k_mem_partition_attr_t;
 
#define K_MEM_PARTITION_IS_EXECUTABLE(attr)     (((attr) & XTENSA_MMU_PERM_X) != 0)
#define K_MEM_PARTITION_IS_WRITABLE(attr)       (((attr) & XTENSA_MMU_PERM_W) != 0)
#define K_MEM_PARTITION_IS_USER(attr)           (((attr) & XTENSA_MMU_MAP_USER) != 0)
 
/* Read-Write access permission attributes */
#define K_MEM_PARTITION_P_RW_U_RW \
        ((k_mem_partition_attr_t) {XTENSA_MMU_PERM_W | XTENSA_MMU_MAP_USER})
#define K_MEM_PARTITION_P_RW_U_NA \
        ((k_mem_partition_attr_t) {0})
#define K_MEM_PARTITION_P_RO_U_RO \
        ((k_mem_partition_attr_t) {XTENSA_MMU_MAP_USER})
#define K_MEM_PARTITION_P_RO_U_NA \
        ((k_mem_partition_attr_t) {0})
#define K_MEM_PARTITION_P_NA_U_NA \
        ((k_mem_partition_attr_t) {0})
 
/* Execution-allowed attributes */
#define K_MEM_PARTITION_P_RX_U_RX \
        ((k_mem_partition_attr_t) {XTENSA_MMU_PERM_X})
 
#define XTENSA_MMU_MAP_USER             BIT(4)
 
#define XTENSA_MMU_MAP_SHARED           BIT(30)
 
struct xtensa_mmu_range {
        const char *name;
 
        const uint32_t start;
 
        const uint32_t end;
 
        const uint32_t attrs;
};
 
extern const struct xtensa_mmu_range xtensa_soc_mmu_ranges[];
 
extern int xtensa_soc_mmu_ranges_num;
 
void xtensa_mmu_init(void);
 
void xtensa_mmu_tlb_ipi(void);
 
void xtensa_mmu_tlb_shootdown(void);
 
#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MMU_H */