Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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barrier.h
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1/*
2 * Copyright (c) 2023 Carlo Caione <[email protected]>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_SYS_BARRIER_H_
8#define ZEPHYR_INCLUDE_SYS_BARRIER_H_
9
10#include <zephyr/toolchain.h>
11
12#if defined(CONFIG_BARRIER_OPERATIONS_ARCH)
13# if defined(CONFIG_ARM)
15# elif defined(CONFIG_ARM64)
17# endif
18#elif defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
20#endif
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
41{
42#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
43 z_barrier_dmem_fence_full();
44#endif
45}
46
60{
61#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
62 z_barrier_dsync_fence_full();
63#endif
64}
65
79{
80#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
81 z_barrier_isync_fence_full();
82#endif
83}
84
87#ifdef __cplusplus
88} /* extern "C" */
89#endif
90
91#endif /* ZEPHYR_INCLUDE_SYS_ATOMIC_H_ */
#define ALWAYS_INLINE
Definition: common.h:129
static ALWAYS_INLINE void barrier_isync_fence_full(void)
Full/sequentially-consistent instruction synchronization barrier.
Definition: barrier.h:78
static ALWAYS_INLINE void barrier_dsync_fence_full(void)
Full/sequentially-consistent data synchronization barrier.
Definition: barrier.h:59
static ALWAYS_INLINE void barrier_dmem_fence_full(void)
Full/sequentially-consistent data memory barrier.
Definition: barrier.h:40
Macros to abstract toolchain specific capabilities.