Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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exception.h
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1/*
2 * Copyright (c) 2016 Jean-Paul Etienne <[email protected]>
3 * Copyright (c) 2018 Foundries.io Ltd
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
15#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_EXCEPTION_H_
16#define ZEPHYR_INCLUDE_ARCH_RISCV_EXCEPTION_H_
17
18#ifndef _ASMLANGUAGE
19#include <zephyr/types.h>
20#include <zephyr/toolchain.h>
21
22#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
23#include <soc_context.h>
24#endif
25
26#ifdef CONFIG_RISCV_SOC_HAS_ISR_STACKING
27#include <soc_isr_stacking.h>
28#endif
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34/*
35 * The name of the structure which contains soc-specific state, if
36 * any, as well as the soc_esf_t typedef below, are part of the RISC-V
37 * arch API.
38 *
39 * The contents of the struct are provided by a SOC-specific
40 * definition in soc_context.h.
41 */
42#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
43struct soc_esf {
44 SOC_ESF_MEMBERS;
45};
46#endif
47
48#if defined(CONFIG_RISCV_SOC_HAS_ISR_STACKING)
49 SOC_ISR_STACKING_ESF_DECLARE;
50#else
51struct __esf {
52 unsigned long ra; /* return address */
53
54 unsigned long t0; /* Caller-saved temporary register */
55 unsigned long t1; /* Caller-saved temporary register */
56 unsigned long t2; /* Caller-saved temporary register */
57#if !defined(CONFIG_RISCV_ISA_RV32E)
58 unsigned long t3; /* Caller-saved temporary register */
59 unsigned long t4; /* Caller-saved temporary register */
60 unsigned long t5; /* Caller-saved temporary register */
61 unsigned long t6; /* Caller-saved temporary register */
62#endif /* !CONFIG_RISCV_ISA_RV32E */
63
64 unsigned long a0; /* function argument/return value */
65 unsigned long a1; /* function argument */
66 unsigned long a2; /* function argument */
67 unsigned long a3; /* function argument */
68 unsigned long a4; /* function argument */
69 unsigned long a5; /* function argument */
70#if !defined(CONFIG_RISCV_ISA_RV32E)
71 unsigned long a6; /* function argument */
72 unsigned long a7; /* function argument */
73#endif /* !CONFIG_RISCV_ISA_RV32E */
74
75 unsigned long mepc; /* machine exception program counter */
76 unsigned long mstatus; /* machine status register */
77
78 unsigned long s0; /* callee-saved s0 */
79
80#ifdef CONFIG_USERSPACE
81 unsigned long sp; /* preserved (user or kernel) stack pointer */
82#endif
83
84#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
85 struct soc_esf soc_context;
86#endif
87} __aligned(16);
88#endif /* CONFIG_RISCV_SOC_HAS_ISR_STACKING */
89
90typedef struct __esf z_arch_esf_t;
91#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
92typedef struct soc_esf soc_esf_t;
93#endif
94
95#ifdef __cplusplus
96}
97#endif
98
99#endif /* _ASMLANGUAGE */
100
101#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_EXCEPTION_H_ */
Macros to abstract toolchain specific capabilities.