doxygen/html/gd32f3x0-clocks_8h_source.html

/*

 * Copyright (c) 2022 Teslabs Engineering S.L.

 *

 * SPDX-License-Identifier: Apache-2.0

 */


#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_

#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_


#include "gd32-clocks-common.h"


#define GD32_AHBEN_OFFSET        0x14U

#define GD32_APB1EN_OFFSET       0x1CU

#define GD32_APB2EN_OFFSET       0x18U

#define GD32_ADDAPB1EN_OFFSET    0xF8U


/* AHB peripherals */

#define GD32_CLOCK_DMA        GD32_CLOCK_CONFIG(AHBEN, 0U)

#define GD32_CLOCK_SRAMSP     GD32_CLOCK_CONFIG(AHBEN, 2U)

#define GD32_CLOCK_FMCSP      GD32_CLOCK_CONFIG(AHBEN, 4U)

#define GD32_CLOCK_CRC        GD32_CLOCK_CONFIG(AHBEN, 6U)

#define GD32_CLOCK_USBFS      GD32_CLOCK_CONFIG(AHBEN, 12U)

#define GD32_CLOCK_GPIOA      GD32_CLOCK_CONFIG(AHBEN, 17U)

#define GD32_CLOCK_GPIOB      GD32_CLOCK_CONFIG(AHBEN, 18U)

#define GD32_CLOCK_GPIOC      GD32_CLOCK_CONFIG(AHBEN, 19U)

#define GD32_CLOCK_GPIOD      GD32_CLOCK_CONFIG(AHBEN, 20U)

#define GD32_CLOCK_GPIOF      GD32_CLOCK_CONFIG(AHBEN, 22U)

#define GD32_CLOCK_TSI        GD32_CLOCK_CONFIG(AHBEN, 24U)


/* APB1 peripherals */

#define GD32_CLOCK_TIMER1     GD32_CLOCK_CONFIG(APB1EN, 0U)

#define GD32_CLOCK_TIMER2     GD32_CLOCK_CONFIG(APB1EN, 1U)

#define GD32_CLOCK_TIMER5     GD32_CLOCK_CONFIG(APB1EN, 4U)

#define GD32_CLOCK_TIMER13    GD32_CLOCK_CONFIG(APB1EN, 8U)

#define GD32_CLOCK_WWDGT      GD32_CLOCK_CONFIG(APB1EN, 11U)

#define GD32_CLOCK_SPI1       GD32_CLOCK_CONFIG(APB1EN, 14U)

#define GD32_CLOCK_USART1     GD32_CLOCK_CONFIG(APB1EN, 17U)

#define GD32_CLOCK_I2C0       GD32_CLOCK_CONFIG(APB1EN, 21U)

#define GD32_CLOCK_I2C1       GD32_CLOCK_CONFIG(APB1EN, 22U)

#define GD32_CLOCK_PMU        GD32_CLOCK_CONFIG(APB1EN, 28U)

#define GD32_CLOCK_DAC        GD32_CLOCK_CONFIG(APB1EN, 29U)

#define GD32_CLOCK_CEC        GD32_CLOCK_CONFIG(APB1EN, 30U)


/* APB2 peripherals */

#define GD32_CLOCK_CFGCMP     GD32_CLOCK_CONFIG(APB2EN, 0U)

#define GD32_CLOCK_ADC        GD32_CLOCK_CONFIG(APB2EN, 9U)

#define GD32_CLOCK_TIMER0     GD32_CLOCK_CONFIG(APB2EN, 11U)

#define GD32_CLOCK_SPI0       GD32_CLOCK_CONFIG(APB2EN, 12U)

#define GD32_CLOCK_USART0     GD32_CLOCK_CONFIG(APB2EN, 14U)

#define GD32_CLOCK_TIMER14    GD32_CLOCK_CONFIG(APB2EN, 16U)

#define GD32_CLOCK_TIMER15    GD32_CLOCK_CONFIG(APB2EN, 17U)

#define GD32_CLOCK_TIMER16    GD32_CLOCK_CONFIG(APB2EN, 18U)


/* APB1 additional peripherals */

#define GD32_CLOCK_CTC        GD32_CLOCK_CONFIG(ADDAPB1EN, 27U)


#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_ */

gd32-clocks-common.h