nxp,mipi-dsi-2l

Vendor: NXP Semiconductors

Description

These nodes are “mipi-dsi” bus nodes.

NXP MCUX MIPI DSI 2L

Properties

Properties not inherited from the base binding file.

Name

Type

Details

phy-clock

int

 
MIPI PHY clock frequency. Should be set to ensure clock frequency is at least (pixel clock * bits per output pixel) / number of mipi data lanes

nxp,lcdif

phandle

 
Instance of the LCDIF peripheral. Only required when using the MIPI in video mode

dpi-color-coding

string

 
MIPI DPI interface color coding. Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification.

Legal values: '16-bit-config-1', '16-bit-config-2', '16-bit-config-3', '18-bit-config-1', '18-bit-config-2', '24-bit'

dpi-pixel-packet

string

 
MIPI DSI pixel packet type send through DPI interface.

Legal values: '16-bit', '18-bit', '18-bit-loose', '24-bit'

dpi-video-mode

string

 
DPI video mode.

Legal values: 'non-burst-sync-pulse', 'non-burst-sync-event', 'burst'

dpi-bllp-mode

string

 
Behavior in BLLP (Blanking or Low-Power Interval).

Legal values: 'low-power', 'blank', 'null'

autoinsert-eotp

boolean

 
Automatically insert an EoTp short packet when switching from HS to LP mode.

dphy-ref-frequency

int

 
Maximum clock speed supported by the device, in Hz. Leave at default if no DPHY PLL is present

noncontinuous-hs-clk

boolean

 
Enable non-contiuous high speed clock. Saves power but introduces latency when transitioning to high speed mode.