QSPI HAL

group nrf_qspi_hal

Hardware access layer for managing the QSPI peripheral.

Defines

NRF_QSPI_HAS_XIPEN

Symbol indicating whether XIP can be explicitly enabled or disabled via XIPEN register.

NRF_QSPI_HAS_XIP_ENC

Symbol indicating whether encryption for XIP is present.

NRF_QSPI_HAS_DMA_ENC

Symbol indicating whether encryption for EasyDMA is present.

NRF_QSPI_HAS_MODE_1

Symbol indicating whether support for QSPI mode 1 is present.

NRF_QSPI_BASE_CLOCK_FREQ

Value representing QSPI base clock frequency.

NRF_QSPI_PIN_NOT_CONNECTED

This value can be used as a parameter for the nrf_qspi_pins_set function to specify that a given QSPI signal (SCK, CSN, IO0, IO1, IO2, or IO3) will not be connected to a physical pin.

NRF_QSPI_PIN_VAL(pin)

Macro for setting proper values to pin registers.

Enums

enum nrf_qspi_task_t

QSPI tasks.

Values:

enumerator NRF_QSPI_TASK_ACTIVATE

Activate the QSPI interface.

enumerator NRF_QSPI_TASK_READSTART

Start transfer from external flash memory to internal RAM.

enumerator NRF_QSPI_TASK_WRITESTART

Start transfer from internal RAM to external flash memory.

enumerator NRF_QSPI_TASK_ERASESTART

Start external flash memory erase operation.

enumerator NRF_QSPI_TASK_DEACTIVATE

Deactivate the QSPI interface.

enum nrf_qspi_event_t

QSPI events.

Values:

enumerator NRF_QSPI_EVENT_READY

QSPI peripheral is ready after it executes any task.

enum nrf_qspi_int_mask_t

QSPI interrupts.

Values:

enumerator NRF_QSPI_INT_READY_MASK

Interrupt on READY event.

enum nrf_qspi_frequency_t

QSPI base clock frequency divider values.

Values:

enumerator NRF_QSPI_FREQ_DIV1

Divide by 1.

enumerator NRF_QSPI_FREQ_DIV2

Divide by 2.

enumerator NRF_QSPI_FREQ_DIV3

Divide by 3.

enumerator NRF_QSPI_FREQ_DIV4

Divide by 4.

enumerator NRF_QSPI_FREQ_DIV5

Divide by 5.

enumerator NRF_QSPI_FREQ_DIV6

Divide by 6.

enumerator NRF_QSPI_FREQ_DIV7

Divide by 7.

enumerator NRF_QSPI_FREQ_DIV8

Divide by 8.

enumerator NRF_QSPI_FREQ_DIV9

Divide by 9.

enumerator NRF_QSPI_FREQ_DIV10

Divide by 10.

enumerator NRF_QSPI_FREQ_DIV11

Divide by 11.

enumerator NRF_QSPI_FREQ_DIV12

Divide by 12.

enumerator NRF_QSPI_FREQ_DIV13

Divide by 13.

enumerator NRF_QSPI_FREQ_DIV14

Divide by 14.

enumerator NRF_QSPI_FREQ_DIV15

Divide by 15.

enumerator NRF_QSPI_FREQ_DIV16

Divide by 16.

enum nrf_qspi_readoc_t

Interface configuration for a read operation.

Values:

enumerator NRF_QSPI_READOC_FASTREAD

Single data line SPI. FAST_READ (opcode 0x0B).

enumerator NRF_QSPI_READOC_READ2O

Dual data line SPI. READ2O (opcode 0x3B).

enumerator NRF_QSPI_READOC_READ2IO

Dual data line SPI. READ2IO (opcode 0xBB).

enumerator NRF_QSPI_READOC_READ4O

Quad data line SPI. READ4O (opcode 0x6B).

enumerator NRF_QSPI_READOC_READ4IO

Quad data line SPI. READ4IO (opcode 0xEB).

enum nrf_qspi_writeoc_t

Interface configuration for a write operation.

Values:

enumerator NRF_QSPI_WRITEOC_PP

Single data line SPI. PP (opcode 0x02).

enumerator NRF_QSPI_WRITEOC_PP2O

Dual data line SPI. PP2O (opcode 0xA2).

enumerator NRF_QSPI_WRITEOC_PP4O

Quad data line SPI. PP4O (opcode 0x32).

enumerator NRF_QSPI_WRITEOC_PP4IO

Quad data line SPI. READ4O (opcode 0x38).

enum nrf_qspi_addrmode_t

Interface configuration for addressing mode.

Values:

enumerator NRF_QSPI_ADDRMODE_24BIT

24-bit addressing.

enumerator NRF_QSPI_ADDRMODE_32BIT

32-bit addressing.

enum nrf_qspi_spi_mode_t

QSPI SPI mode. Polarization and phase configuration.

Values:

enumerator NRF_QSPI_MODE_0

Mode 0 (CPOL=0, CPHA=0).

enumerator NRF_QSPI_MODE_1

Mode 1 (CPOL=1, CPHA=1).

enum nrf_qspi_addrconfig_mode_t

Addressing configuration mode.

Values:

enumerator NRF_QSPI_ADDRCONF_MODE_NOINSTR

Do not send any instruction.

enumerator NRF_QSPI_ADDRCONF_MODE_OPCODE

Send opcode.

enumerator NRF_QSPI_ADDRCONF_MODE_OPBYTE0

Send opcode, byte0.

enumerator NRF_QSPI_ADDRCONF_MODE_ALL

Send opcode, byte0, byte1.

enum nrf_qspi_erase_len_t

Erasing data length.

Values:

enumerator NRF_QSPI_ERASE_LEN_4KB

Erase 4 kB block (flash command 0x20).

enumerator NRF_QSPI_ERASE_LEN_64KB

Erase 64 kB block (flash command 0xD8).

enumerator NRF_QSPI_ERASE_LEN_ALL

Erase all (flash command 0xC7).

enum nrf_qspi_cinstr_len_t

Custom instruction length.

Values:

enumerator NRF_QSPI_CINSTR_LEN_1B

Send opcode only.

enumerator NRF_QSPI_CINSTR_LEN_2B

Send opcode, CINSTRDAT0.BYTE0.

enumerator NRF_QSPI_CINSTR_LEN_3B

Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1.

enumerator NRF_QSPI_CINSTR_LEN_4B

Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2.

enumerator NRF_QSPI_CINSTR_LEN_5B

Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3.

enumerator NRF_QSPI_CINSTR_LEN_6B

Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4.

enumerator NRF_QSPI_CINSTR_LEN_7B

Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5.

enumerator NRF_QSPI_CINSTR_LEN_8B

Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6.

enumerator NRF_QSPI_CINSTR_LEN_9B

Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7.

Functions

NRF_STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type *p_reg, nrf_qspi_task_t task)

Function for activating the specified QSPI task.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• task – [in] Task to be activated.

NRF_STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const *p_reg, nrf_qspi_task_t task)

Function for getting the address of the specified QSPI task register.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• task – [in] QSPI task.

Returns:

Address of the specified task register.

NRF_STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type *p_reg, nrf_qspi_event_t event)

Function for clearing the specified QSPI event.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• event – [in] Event to be cleared.

NRF_STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const *p_reg, nrf_qspi_event_t event)

Function for retrieving the state of the QSPI event.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• event – [in] Event to be checked.

Return values:

• true – The event has been generated.

• false – The event has not been generated.

NRF_STATIC_INLINE uint32_t nrf_qspi_event_address_get(NRF_QSPI_Type const *p_reg, nrf_qspi_event_t event)

Function for getting the address of the specified QSPI event register.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• event – [in] The specified event.

Returns:

Address of the specified event register.

NRF_STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type *p_reg, uint32_t mask)

Function for enabling specified interrupts.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• mask – [in] Mask of interrupts to be enabled. Use nrf_qspi_int_mask_t values for bit masking.

NRF_STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type *p_reg, uint32_t mask)

Function for disabling specified interrupts.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• mask – [in] Mask of interrupts to be disabled. Use nrf_qspi_int_mask_t values for bit masking.

NRF_STATIC_INLINE uint32_t nrf_qspi_int_enable_check(NRF_QSPI_Type const *p_reg, uint32_t mask)

Function for checking if the specified interrupts are enabled.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• mask – [in] Mask of interrupts to be checked. Use nrf_qspi_int_mask_t values for bit masking.

Returns:

Mask of enabled interrupts.

NRF_STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type *p_reg)

Function for enabling the QSPI peripheral.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

NRF_STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type *p_reg)

Function for disabling the QSPI peripheral.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

NRF_STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type *p_reg, nrf_qspi_pins_t const *p_pins)

Function for configuring QSPI pins.

If a given signal is not needed, pass the NRF_QSPI_PIN_NOT_CONNECTED value instead of its pin number.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• p_pins – [in] Pointer to the pins configuration structure. See nrf_qspi_pins_t.

NRF_STATIC_INLINE void nrf_qspi_pins_get(NRF_QSPI_Type const *p_reg, nrf_qspi_pins_t *p_pins)

Function for getting the currently configured QSPI pins.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• p_pins – [out] Pointer to the pins configuration structure to be filled with QSPI pins.

NRF_STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type *p_reg, uint32_t xip_offset)

Function for setting the QSPI XIPOFFSET register.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• xip_offset – [in] Address offset in the external memory for Execute in Place operation.

NRF_STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type *p_reg, nrf_qspi_prot_conf_t const *p_config)

Function for setting the QSPI IFCONFIG0 register.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• p_config – [in] Pointer to the QSPI protocol interface configuration structure. See nrf_qspi_prot_conf_t.

NRF_STATIC_INLINE void nrf_qspi_ifconfig0_raw_set(NRF_QSPI_Type *p_reg, uint32_t regval)

Function for setting the explicit value of the QSPI IFCONFIG0 register.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• regval – [in] Register value to be set.

NRF_STATIC_INLINE uint32_t nrf_qspi_ifconfig0_raw_get(NRF_QSPI_Type const *p_reg)

Function for getting the explicit value of the QSPI IFCONFIG0 register.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

Returns:

Value of IFCONFIG0 register.

NRF_STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type *p_reg, nrf_qspi_phy_conf_t const *p_config)

Function for setting the QSPI IFCONFIG1 register.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• p_config – [in] Pointer to the QSPI physical interface configuration structure. See nrf_qspi_phy_conf_t.

NRF_STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type *p_reg, nrf_qspi_addrconfig_conf_t const *p_config)

Function for setting the QSPI ADDRCONF register.

This function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure is sent during the start of the peripheral. Remember that the reset instruction can set addressing mode to default in the memory device. If memory reset is necessary before configuring the addressing mode, use custom instruction feature instead of this function. Case with reset: Enable the peripheral without setting ADDRCONF register, send reset instructions using a custom instruction feature (reset enable and then reset), set proper addressing mode using the custom instruction feature.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• p_config – [in] Pointer to the addressing mode configuration structure. See nrf_qspi_addrconfig_conf_t.

NRF_STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type *p_reg, void const *p_buffer, uint32_t length, uint32_t dest_addr)

Function for setting write data into the peripheral register (without starting the process).

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• p_buffer – [in] Pointer to the writing buffer.

• length – [in] Lenght of the writing data.

• dest_addr – [in] Address in memory to write to.

NRF_STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type *p_reg, void *p_buffer, uint32_t length, uint32_t src_addr)

Function for setting read data into the peripheral register (without starting the process).

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• p_buffer – [out] Pointer to the reading buffer.

• length – [in] Length of the read data.

• src_addr – [in] Address in memory to read from.

NRF_STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type *p_reg, uint32_t erase_addr, nrf_qspi_erase_len_t len)

Function for setting erase data into the peripheral register (without starting the process).

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• erase_addr – [in] Start address to erase. Address must have padding set to 4 bytes.

• len – [in] Size of erasing area.

NRF_STATIC_INLINE uint32_t nrf_qspi_erase_ptr_get(NRF_QSPI_Type const *p_reg)

Function for getting the currently configured erase pointer.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

Returns:

Erase pointer.

NRF_STATIC_INLINE nrf_qspi_erase_len_t nrf_qspi_erase_len_get(NRF_QSPI_Type const *p_reg)

Function for getting the currently configured erase length.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

Returns:

Erase length.

NRF_STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const *p_reg)

Function for getting the peripheral status register.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

Returns:

Peripheral status register.

NRF_STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const *p_reg)

Function for getting the device status register stored in the peripheral status register.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

Returns:

Device status register (lower byte).

NRF_STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const *p_reg)

Function for checking if the peripheral is busy or not.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

Return values:

• true – The QSPI is busy.

• false – The QSPI is ready.

NRF_STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type *p_reg, nrf_qspi_cinstr_len_t length, void const *p_tx_data)

Function for setting registers sending with custom instruction transmission.

This function can be ommited when using NRF_QSPI_CINSTR_LEN_1B as the length argument (sending only opcode without data).

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• length – [in] Length of the custom instruction data.

• p_tx_data – [in] Pointer to the data to send with the custom instruction.

NRF_STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const *p_reg, nrf_qspi_cinstr_len_t length, void *p_rx_data)

Function for getting data from register after custom instruction transmission.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• length – [in] Length of the custom instruction data.

• p_rx_data – [in] Pointer to the reading buffer.

NRF_STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type *p_reg, nrf_qspi_cinstr_conf_t const *p_config)

Function for sending custom instruction to external memory.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• p_config – [in] Pointer to the custom instruction configuration structure. See nrf_qspi_cinstr_conf_t.

NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type *p_reg, nrf_qspi_cinstr_conf_t const *p_config)

Function for starting a custom instruction long transfer.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• p_config – [in] Pointer to the custom instruction configuration structure. See nrf_qspi_cinstr_conf_t.

NRF_STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const *p_reg)

Function for checking whether a custom instruction long transfer is ongoing.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

Return values:

• true – Custom instruction long transfer is ongoing.

• false – Custom instruction long transfer is not ongoing.

NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type *p_reg, nrf_qspi_cinstr_len_t length, bool finalize)

Function for continuing a custom instruction long transfer.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• length – [in] Length of the custom instruction data.

• finalize – [in] True if the custom instruction long transfer is to be finalized. False if the custom instruction long transfer is to be continued.

NRF_STATIC_INLINE void nrf_qspi_xip_set(NRF_QSPI_Type *p_reg, bool enable)

Function for enabling or disabling Execute in Place (XIP) operation.

Note

XIP can be enabled after reset. See Product Specification.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• enable – [in] True if XIP is to be enabled, false otherwise.

NRF_STATIC_INLINE void nrf_qspi_xip_encryption_configure(NRF_QSPI_Type *p_reg, nrf_qspi_encryption_t const *p_cfg)

Function for configuring the XIP encryption.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• p_cfg – [in] Pointer to encryption configuration structure.

NRF_STATIC_INLINE void nrf_qspi_xip_encryption_set(NRF_QSPI_Type *p_reg, bool enable)

Function for enabling or disabling the XIP encryption.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• enable – [in] True if XIP encryption is to be enabled, false otherwise.

NRF_STATIC_INLINE void nrf_qspi_dma_encryption_configure(NRF_QSPI_Type *p_reg, nrf_qspi_encryption_t const *p_cfg)

Function for configuring the EasyDMA encryption.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• p_cfg – [in] Pointer to encryption configuration structure.

NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type *p_reg, bool enable)

Function for enabling or disabling the EasyDMA encryption.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• enable – [in] True if EasyDMA encryption is to be enabled, false otherwise.

NRF_STATIC_INLINE void nrf_qspi_iftiming_set(NRF_QSPI_Type *p_reg, uint8_t rxdelay)

Function for setting the timing related to sampling of the input serial data.

Parameters:

• p_reg – [in] Pointer to the structure of registers of the peripheral.

• rxdelay – [in] Number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the clock until the input serial data is sampled.

struct nrf_qspi_pins_t

#include <nrf_qspi.h>

Pin configuration.

Public Members

uint32_t sck_pin

SCK pin number.

uint32_t csn_pin

Chip select pin number.

uint32_t io0_pin

IO0/MOSI pin number.

uint32_t io1_pin

IO1/MISO pin number.

uint32_t io2_pin

IO2 pin number (optional). Set to NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.

uint32_t io3_pin

IO3 pin number (optional). Set to NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.

struct nrf_qspi_cinstr_conf_t

#include <nrf_qspi.h>

Custom instruction configuration.

Public Members

uint8_t opcode

Opcode used in custom instruction transmission.

nrf_qspi_cinstr_len_t length

Length of the custom instruction data.

bool io2_level

I/O line level during transmission.

bool io3_level

I/O line level during transmission.

bool wipwait

Wait if a Wait in Progress bit is set in the memory status byte.

bool wren

Send write enable before instruction.

struct nrf_qspi_addrconfig_conf_t

#include <nrf_qspi.h>

Addressing mode register configuration. See nrf_qspi_addrconfig_set.

Public Members

uint8_t opcode

Opcode used to enter the proper addressing mode.

uint8_t byte0

Byte following the opcode.

uint8_t byte1

Byte following byte0.

nrf_qspi_addrconfig_mode_t mode

Extended addresing mode.

bool wipwait

Enable or disable waiting for complete operation execution.

bool wren

Send write enable before instruction.

struct nrf_qspi_prot_conf_t

#include <nrf_qspi.h>

Structure with QSPI protocol interface configuration.

Public Members

nrf_qspi_readoc_t readoc

Read operation code.

nrf_qspi_writeoc_t writeoc

Write operation code.

nrf_qspi_addrmode_t addrmode

Addresing mode (24-bit or 32-bit).

bool dpmconfig

Enable the Deep Power-down Mode (DPM) feature.

struct nrf_qspi_phy_conf_t

#include <nrf_qspi.h>

QSPI physical interface configuration.

Public Members

uint8_t sck_delay

tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns).

bool dpmen

Enable the DPM feature.

nrf_qspi_spi_mode_t spi_mode

SPI phase and polarization.

nrf_qspi_frequency_t sck_freq

SCK frequency given as QSPI base clock frequency divider. To calculate sck_freq value corresponding to chosen frequency, use the following equation:

sck_freq = (NRF_QSPI_BASE_CLOCK_FREQ / frequency) - 1

Note

Achievable frequencies are determined by available divider values and QSPI base clock frequency.

struct nrf_qspi_encryption_t

#include <nrf_qspi.h>

QSPI encryption settings for XIP and DMA transfers.

Public Members

uint32_t key[4]

AES 128-bit key, stored on 4 32-bit words.

uint32_t nonce[3]

AES 96-bit nonce, stored on 3 32-bit words.