nuvoton,numicro-pinctrl
Vendor: Nuvoton Technology Corporation
Description
Nuvoton NuMicro pinctrl node. This node will define pin configurations in pin groups,
and has the 'pinctrl' node identifier in the SOC's devicetree. Each group
within the pin configuration defines the pin configuration for a peripheral,
and each numbered subgroup in the pin group defines all the pins for that
peripheral with the same configuration properties. The 'pinmux' property in
a group selects the pins to be configured, and the remaining properties set
configuration values for those pins. Here is an example group for UART0 pins:
uart0_default: uart0_default {
group0 {
pinmux = <UART0_RXD_PB12>, <UART0_TXD_PB13>;
};
};
Properties
Top level properties
These property descriptions apply to “nuvoton,numicro-pinctrl” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
(None)
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “nuvoton,numicro-pinctrl” compatible.
Name |
Type |
Details |
|---|---|---|
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register space
This property is required. See Important properties for more information. |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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name of each register space
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interrupts for device
See Important properties for more information. |
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extended interrupt specifier for device
|
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name of each interrupt
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phandle to interrupt controller node
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Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. This property is deprecated. |
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
|
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Automatically configure the device for runtime power management after the
init function runs.
|
Grandchild node properties
Name |
Type |
Details |
|---|---|---|
|
|
Pin mux selections for this group. See the SoC level pinctrl dtsi file
for a defined list of these options.
This property is required. |
|
|
Pin output slew rate. Sets the HSRENx register. If not set, defaults to the
reset value (normal).
Default value: Legal values: |
|
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enable the input debounce function
|
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enable pull-up resistor
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enable pull-down resistor
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drive with open drain (hardware AND)
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disable input on pin (e.g. disable an input buffer, no effect on output)
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enable schmitt-trigger mode
|