st,stm32f100-pll-clock

Vendor: STMicroelectronics

Description

Main PLL node binding for STM32F100 devices

Takes one of clk_hse or clk_hsi as input clock.
When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
pll2, configurable prescaler is used.

Up to 2 output clocks could be supported and for each output clock, the
frequency can be computed with the following formula:

  f(PLLCLK) = f(PLLIN) x PLLMUL       --> SYSCLK (System Clock)

  with, depending on the case:
          f(PLLIN) = f(input_clk) / 2       if input_clk = clk_hsi
          f(PLLIN) = f(input_clk) / PREDIV  if input_clk = clk_hse

The PLL output frequency must not exceed 24 MHz.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

mul

int

 
PLL multiplication factor for output clock
Valid range: 2 - 16

This property is required.

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

prediv

int

 
Configurable prescaler
Valid range: 1 - 16

This property is required.

otgfspre

boolean

 
Otpional PLL output divisor to generate a 48MHz USB clock.
When set, PLL output clock is not divided.
Otherwise, PLL output clock is divided by 1.5.