infineon,xmc4xxx-uart
Vendor: Infineon Technologies
Description
These nodes are “uart” bus nodes.
INFINEON XMC4XXX UART
Properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
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Connects the UART receive line (USIC DX0 input) to a specific GPIO pin.
The USIC DX0 input is a multiplexer which connects to different GPIO pins.
Refer to the XMC4XXX reference manual for the GPIO pin/mux mappings. DX0G
is the loopback input line.
This property is required. Legal values: |
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Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.
This property is required. |
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Names for the provided states. The number of names needs to match the
number of states.
This property is required. |
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Each USIC0..2 has a fifo that is shared between two channels. For example,
usic0ch0 and usic0ch1 will share the same fifo. This parameter defines an offset
where the tx and rx fifos will start. When sharing the fifo, the user must properly
define the offset based on the configuration of the other channel. The fifo has a
capacity of 64 entries. The tx/rx fifos are created on fifo-xx-size aligned
boundaries.
This property is required. |
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Fifo size used for buffering transmit bytes. A value of 0 implies that
the fifo is not used while transmitting.
This property is required. Legal values: |
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Fifo size used for buffering received bytes. A value of 0 implies that
the fifo is not used while receiving.
This property is required. Legal values: |
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Clock frequency information for UART operation
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Initial baud rate setting for UART
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Set to enable RTS/CTS flow control at boot time
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Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd
and 2 for even parity. Default to none if not specified.
Legal values: |
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Pin configuration/s for the second state. See pinctrl-0.
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Pin configuration/s for the third state. See pinctrl-0.
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Pin configuration/s for the fourth state. See pinctrl-0.
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Pin configuration/s for the fifth state. See pinctrl-0.
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Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “infineon,xmc4xxx-uart” compatible.
Name |
Type |
Details |
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register space
This property is required. See Important properties for more information. |
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IRQ number and priority to use for interrupt driven UART.
USIC0..2 have their own interrupt range as follows:
USIC0 = [84, 89]
USIC1 = [90, 95]
USIC2 = [96, 101]
See Important properties for more information. |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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name of each register space
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. This property is deprecated. |
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
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