nxp,rt-iocon-pinctrl
Vendor: NXP Semiconductors
Description
RT600/RT500 pin control node. This node defines pin configurations in pin
groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
group within the pin configuration defines a peripheral's pin configuration.
Each numbered subgroup represents pins with shared configuration for that
peripheral. The 'pinmux' property of each group selects the pins to be
configured with these properties. For example, here is a configuration
for FLEXCOMM0 pins:
pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
group0 {
pinmux = <FC0_TXD_SCL_MISO_WS_PIO0_1>,
<FC0_RXD_SDA_MOSI_DATA_PIO0_2>;
slew-rate = "normal";
drive-strength = "normal";
};
};
If only the required properties are supplied, the ICON_PIO register will
be assigned the following values:
IOCON_FUNC=<pin mux selection>,
IOCON_PUPDENA = 0,
IOCON_PUPDSEL = 0,
IOCON_IBENA = 0,
IOCON_SLEWRATE = <slew-rate selection>,
IOCON_FULLDRIVE = <drive-strength selection>,
IOCON_AMENA = 0,
IOCON_ODENA = 0,
IOCON_IIENA = 0,
Note the inherited pinctrl properties defined below have the following effects:
drive-open-drain: IOCON_ODENA=1
bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0
input-enable: IOCON_IBENA=1
Properties
Top level properties
These property descriptions apply to “nxp,rt-iocon-pinctrl” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
(None)
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “nxp,rt-iocon-pinctrl” compatible.
Name |
Type |
Details |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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register space
See Important properties for more information. |
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name of each register space
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interrupts for device
See Important properties for more information. |
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. This property is deprecated. |
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
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Grandchild node properties
Name |
Type |
Details |
|---|---|---|
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Pin mux selection for this group. See the SOC level pinctrl header
file in NXP's HAL for a defined list of these options.
This property is required. |
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Pin output slew rate. Sets the SLEWRATE field in the IOCON register.
0 SLEWRATE_0- normal mode, output slew rate is standard
1 SLEWRATE_1- slow mode, output slew rate is slower
This property is required. Legal values: |
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Pin output drive strength. Sets the FULLDRIVE field in the
IOCON register.
0 FULLDRIVE_0- Normal output drive mode
1 FULLDRIVE_1- Full output drive mode, output strength is twice
the drive strength of normal drive mode.
This property is required. Legal values: |
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Invert the pin input logic level
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Set the pin to analog mode. Sets AMENA=1
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enable pull-up resistor
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enable pull-down resistor
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drive with open drain (hardware AND)
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enable input on pin (no effect on output, such as enabling an input
buffer)
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