nxp,mcux-rt11xx-pinctrl
Vendor: NXP Semiconductors
Description
The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree. These
nodes can be autogenerated using the MCUXpresso config tools combined with
the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
fields in a group select the pins to be configured, and the remaining
devicetree properties set configuration values for those pins
for example, here is an group configuring LPUART1 pins:
group0 {
pinmux = <&iomuxc_gpio_ad_25_lpuart1_rxd>,
<&iomuxc_gpio_ad_24_lpuart1_txd>;
drive-strength = "high";
slew-rate = "slow";
};
This will select GPIO_AD_25 as LPUART1 RX, and GPIO_AD_24 as LPUART1 TX.
Both pins will be configured with a weak latch, high drive strength,
and slow slew rates.
Note that the soc level iomuxc dts file can be examined to find the possible
pinmux options. Here are the affects of each property on the
IOMUXC SW_PAD_CTL register:
drive-open-drain: ODE/ODE_LPSR=1
input-enable: SION=1 (in SW_MUX_CTL_PAD register)
bias-pull-down: PUE=1, PUS=0
bias-pull-up: PUE=1, PUS=1
bias-disable: PULL=11 (in supported registers)
slew-rate: SRE=<enum_idx>
drive-strength: DSE=<enum_idx>
If only required properties are supplied, the pin will have the following
configuration:
ODE=0
SION=0
PUE=0
PUS=0
SRE=0
DSE=0
For registers with PDVR and PULL fields, these are the defaults:
PULL=11
PDRV=0
Properties
Top level properties
These property descriptions apply to “nxp,mcux-rt11xx-pinctrl” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
(None)
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “nxp,mcux-rt11xx-pinctrl” compatible.
Name |
Type |
Details |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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register space
See Important properties for more information. |
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name of each register space
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interrupts for device
See Important properties for more information. |
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. |
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
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Grandchild node properties
Name |
Type |
Details |
|---|---|---|
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Pin mux selections for this group. See the soc level iomuxc DTSI file
for a defined list of these options.
This property is required. |
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Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
0 (normal) - sets pin to normal drive strength
1 (high) - sets pin to high drive strength
Legal values: |
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Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
0 (fast) — Fast Slew Rate
1 (slow) — Slow Slew Rate
Legal values: |
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disable any pin bias
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enable pull-up resistor
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enable pull-down resistor
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drive with open drain (hardware AND)
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enable input on pin (no effect on output, such as enabling an input
buffer)
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