nordic,nrf-spi

Vendor: Nordic Semiconductor

Description

These nodes are “spi” bus nodes.

Nordic nRF family SPI (SPI master)

Properties

Properties not inherited from the base binding file.

Name

Type

Details

miso-pull-up

boolean

 
Enable pull-up on MISO line

miso-pull-down

boolean

 
Enable pull-down on MISO line

sck-pin

int

 
The SCK pin to use.

For pins P0.0 through P0.31, use the pin number. For example,
to use P0.16 for SCK, set:

    sck-pin = <16>;

For pins P1.0 through P1.31, add 32 to the pin number. For
example, to use P1.2 for SCK, set:

    sck-pin = <34>;  /* 32 + 2 */

This property is required.

mosi-pin

int

 
The MOSI pin to use. The pin numbering scheme is the same as
the sck-pin property's.

This property is required.

miso-pin

int

 
The MISO pin to use. The pin numbering scheme is the same as
the sck-pin property's.

This property is required.

clock-frequency

int

 
Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

 
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.