CONFIG_ZERO_LATENCY_IRQS
Enable zero-latency interrupts
Type: bool
Help
The kernel may reserve some of the highest interrupts priorities in
the system for its own use. These interrupts will not be masked
by interrupt locking.
When connecting interrupts the kernel will offset all interrupts
to lower priority than those reserved by the kernel.
Zero-latency interrupt can be used to set up an interrupt at the
highest interrupt priority which will not be blocked by interrupt
locking.
Since Zero-latency ISRs will run in the same priority or possibly at
higher priority than the rest of the kernel they cannot use any
kernel functionality.
Direct dependencies
CPU_CORTEX_M_HAS_BASEPRI
&& (ARMV6_M_ARMV8_M_BASELINE
|| ARMV7_M_ARMV8_M_MAINLINE
) && CPU_CORTEX_M
&& ARM
(Includes any dependencies from ifs and menus.)
Defaults
No defaults. Implicitly defaults to n
.
Symbols that select this symbol
Kconfig definition
At <Zephyr>/arch/arm/core/aarch32/cortex_m/Kconfig:282
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:39
→ <Zephyr>/arch/Kconfig:12
→ <Zephyr>/arch/arm/Kconfig:65
→ <Zephyr>/arch/arm/core/aarch32/Kconfig:305
Menu path: (Top) → ARM Options → ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33 options
config ZERO_LATENCY_IRQS
bool "Enable zero-latency interrupts"
depends on CPU_CORTEX_M_HAS_BASEPRI && (ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE) && CPU_CORTEX_M && ARM
help
The kernel may reserve some of the highest interrupts priorities in
the system for its own use. These interrupts will not be masked
by interrupt locking.
When connecting interrupts the kernel will offset all interrupts
to lower priority than those reserved by the kernel.
Zero-latency interrupt can be used to set up an interrupt at the
highest interrupt priority which will not be blocked by interrupt
locking.
Since Zero-latency ISRs will run in the same priority or possibly at
higher priority than the rest of the kernel they cannot use any
kernel functionality.
(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)