CONFIG_RISCV_PMP

RISC-V PMP Support

Type: bool

Help

MCU implements Physical Memory Protection.
Memory protection against read-only area writing
is natively supported on real HW.

Direct dependencies

RISCV

(Includes any dependencies from ifs and menus.)

Default

n

Symbols selected by this symbol

Symbols that select this symbol

CORE_E31

Kconfig definition

At <Zephyr>/arch/riscv/Kconfig:134

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:39 → <Zephyr>/arch/Kconfig:12

Menu path: (Top) → RISCV Options → RISCV Processor Options

menuconfig RISCV_PMP
    bool "RISC-V PMP Support"
    default n
    select THREAD_STACK_INFO
    select CPU_HAS_MPU
    select MPU
    select SRAM_REGION_PERMISSIONS
    select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
    select PMP_POWER_OF_TWO_ALIGNMENT if USERSPACE
    depends on RISCV
    help
      MCU implements Physical Memory Protection.
      Memory protection against read-only area writing
      is natively supported on real HW.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)