CONFIG_CAVS_TIMER

CAVS DSP Wall Clock Timer on Intel SoC

Type: bool

Help

The DSP wall clock timer is a timer driven directly by
external oscillator and is external to the CPU core(s).
It is not as fast as the internal core clock, but provides
a common and synchronized counter for all CPU cores (which
is useful for SMP).

Direct dependencies

SOC_SERIES_INTEL_CAVS_V15 || SOC_SERIES_INTEL_CAVS_V18 || SOC_SERIES_INTEL_CAVS_V20 || SOC_SERIES_INTEL_CAVS_V25 || (SMP && SOC_INTEL_S1000) || SOC_SERIES_INTEL_CAVS_V15 || SOC_SERIES_INTEL_CAVS_V18 || SOC_SERIES_INTEL_CAVS_V20 || SOC_SERIES_INTEL_CAVS_V25 || (SMP && SOC_INTEL_S1000) || CAVS_ICTL

(Includes any dependencies from ifs and menus.)

Defaults

y
y
y
y
y
y
y
y
y
y

Symbols selected by this symbol

Kconfig definitions

At <Zephyr>/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series:45

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:25 → <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1 → <Zephyr>/soc/xtensa/intel_adsp/Kconfig.defconfig:6

Menu path: (Top)

config CAVS_TIMER
    bool
    default y
    depends on SOC_SERIES_INTEL_CAVS_V15

At <Zephyr>/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series:31

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:25 → <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1 → <Zephyr>/soc/xtensa/intel_adsp/Kconfig.defconfig:6

Menu path: (Top)

config CAVS_TIMER
    bool
    default y
    depends on SOC_SERIES_INTEL_CAVS_V18

At <Zephyr>/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series:31

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:25 → <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1 → <Zephyr>/soc/xtensa/intel_adsp/Kconfig.defconfig:6

Menu path: (Top)

config CAVS_TIMER
    bool
    default y
    depends on SOC_SERIES_INTEL_CAVS_V20

At <Zephyr>/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series:28

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:25 → <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1 → <Zephyr>/soc/xtensa/intel_adsp/Kconfig.defconfig:6

Menu path: (Top)

config CAVS_TIMER
    bool
    default y
    depends on SOC_SERIES_INTEL_CAVS_V25

At <Zephyr>/soc/xtensa/intel_s1000/Kconfig.defconfig:42

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:25 → <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1

Menu path: (Top)

config CAVS_TIMER
    bool
    default y
    depends on SMP && SOC_INTEL_S1000

At <Zephyr>/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series:45

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:27 → <Zephyr>/soc/xtensa/intel_adsp/Kconfig.defconfig:6

Menu path: (Top)

config CAVS_TIMER
    bool
    default y
    depends on SOC_SERIES_INTEL_CAVS_V15

At <Zephyr>/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series:31

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:27 → <Zephyr>/soc/xtensa/intel_adsp/Kconfig.defconfig:6

Menu path: (Top)

config CAVS_TIMER
    bool
    default y
    depends on SOC_SERIES_INTEL_CAVS_V18

At <Zephyr>/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series:31

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:27 → <Zephyr>/soc/xtensa/intel_adsp/Kconfig.defconfig:6

Menu path: (Top)

config CAVS_TIMER
    bool
    default y
    depends on SOC_SERIES_INTEL_CAVS_V20

At <Zephyr>/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series:28

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:27 → <Zephyr>/soc/xtensa/intel_adsp/Kconfig.defconfig:6

Menu path: (Top)

config CAVS_TIMER
    bool
    default y
    depends on SOC_SERIES_INTEL_CAVS_V25

At <Zephyr>/soc/xtensa/intel_s1000/Kconfig.defconfig:42

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:27

Menu path: (Top)

config CAVS_TIMER
    bool
    default y
    depends on SMP && SOC_INTEL_S1000

At <Zephyr>/drivers/timer/Kconfig.cavs:6

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:42 → <Zephyr>/drivers/Kconfig:30 → <Zephyr>/drivers/timer/Kconfig:61

Menu path: (Top) → Device Drivers → Timer Drivers

config CAVS_TIMER
    bool "CAVS DSP Wall Clock Timer on Intel SoC"
    select TICKLESS_CAPABLE
    select TIMER_HAS_64BIT_CYCLE_COUNTER
    depends on CAVS_ICTL
    help
      The DSP wall clock timer is a timer driven directly by
      external oscillator and is external to the CPU core(s).
      It is not as fast as the internal core clock, but provides
      a common and synchronized counter for all CPU cores (which
      is useful for SMP).

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)