CONFIG_SOC_ANDES_V5_L2_CACHE

Enable Andes V5 L2 cache controller

Type: bool

Direct dependencies

(CACHE_ENABLE && SOC_SERIES_RISCV_ANDES_V5) || (CACHE_ENABLE && SOC_SERIES_RISCV_ANDES_V5)

(Includes any dependencies from ifs and menus.)

Defaults

y
y

Kconfig definitions

At <Zephyr>/soc/riscv/riscv-privilege/andes_v5/Kconfig.soc:51

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:38 → <Zephyr>/soc/Kconfig:15 → <nRF>/doc/_build/kconfig/Kconfig.soc.arch:2 → <Zephyr>/soc/riscv/riscv-privilege/Kconfig:22

Menu path: (Top) → Hardware Configuration → Enable cache

config SOC_ANDES_V5_L2_CACHE
    bool "Enable Andes V5 L2 cache controller"
    default y
    depends on CACHE_ENABLE && SOC_SERIES_RISCV_ANDES_V5

At <Zephyr>/soc/riscv/riscv-privilege/andes_v5/Kconfig.soc:51

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:38 → <Zephyr>/soc/Kconfig:18 → <Zephyr>/soc/riscv/riscv-privilege/Kconfig:22

Menu path: (Top) → Hardware Configuration → Enable cache

config SOC_ANDES_V5_L2_CACHE
    bool "Enable Andes V5 L2 cache controller"
    default y
    depends on CACHE_ENABLE && SOC_SERIES_RISCV_ANDES_V5

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)