CONFIG_RISCV_SOC_INTERRUPT_INIT
Enable SOC-based interrupt initialization
Type: bool
Help
Enable SOC-based interrupt initialization
(call soc_interrupt_init, within _IntLibInit when enabled)
Direct dependencies
SOC_OPENISA_RV32M1_RISCV32
|| SOC_SERIES_RISCV_ANDES_V5
|| (SOC_GD32VF103
&& SOC_SERIES_GD32VF103
) || SOC_SERIES_RISCV32_MIV
|| SOC_SERIES_RISCV_SIFIVE_FREEDOM
|| SOC_SERIES_STARFIVE_JH71XX
|| SOC_SERIES_RISCV_TELINK_B91
|| SOC_SERIES_RISCV_VIRT
|| SOC_OPENISA_RV32M1_RISCV32
|| SOC_SERIES_RISCV_ANDES_V5
|| (SOC_GD32VF103
&& SOC_SERIES_GD32VF103
) || SOC_SERIES_RISCV32_MIV
|| SOC_SERIES_RISCV_SIFIVE_FREEDOM
|| SOC_SERIES_STARFIVE_JH71XX
|| SOC_SERIES_RISCV_TELINK_B91
|| SOC_SERIES_RISCV_VIRT
|| RISCV
(Includes any dependencies from ifs and menus.)
Defaults
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
Symbols that select this symbol
Kconfig definitions
At <Zephyr>/soc/riscv/openisa_rv32m1/Kconfig.defconfig:33
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:25
→ <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_OPENISA_RV32M1_RISCV32
At <Zephyr>/soc/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:24
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:25
→ <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_RISCV_ANDES_V5
At <Zephyr>/soc/riscv/riscv-privilege/gd32vf103/Kconfig.defconfig.gd32vf103:21
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:25
→ <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
→ <Zephyr>/soc/riscv/riscv-privilege/gd32vf103/Kconfig.defconfig.series:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_GD32VF103 && SOC_SERIES_GD32VF103
At <Zephyr>/soc/riscv/riscv-privilege/miv/Kconfig.defconfig.series:11
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:25
→ <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_RISCV32_MIV
At <Zephyr>/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:11
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:25
→ <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM
At <Zephyr>/soc/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:12
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:25
→ <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_STARFIVE_JH71XX
At <Zephyr>/soc/riscv/riscv-privilege/telink_b91/Kconfig.defconfig.series:14
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:25
→ <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_RISCV_TELINK_B91
At <Zephyr>/soc/riscv/riscv-privilege/virt/Kconfig.defconfig.series:12
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:25
→ <nRF>/doc/_build/kconfig/Kconfig.soc.defconfig:1
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_RISCV_VIRT
At <Zephyr>/soc/riscv/openisa_rv32m1/Kconfig.defconfig:33
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:27
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_OPENISA_RV32M1_RISCV32
At <Zephyr>/soc/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:24
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:27
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_RISCV_ANDES_V5
At <Zephyr>/soc/riscv/riscv-privilege/gd32vf103/Kconfig.defconfig.gd32vf103:21
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:27
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
→ <Zephyr>/soc/riscv/riscv-privilege/gd32vf103/Kconfig.defconfig.series:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_GD32VF103 && SOC_SERIES_GD32VF103
At <Zephyr>/soc/riscv/riscv-privilege/miv/Kconfig.defconfig.series:11
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:27
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_RISCV32_MIV
At <Zephyr>/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:11
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:27
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM
At <Zephyr>/soc/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:12
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:27
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_STARFIVE_JH71XX
At <Zephyr>/soc/riscv/riscv-privilege/telink_b91/Kconfig.defconfig.series:14
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:27
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_RISCV_TELINK_B91
At <Zephyr>/soc/riscv/riscv-privilege/virt/Kconfig.defconfig.series:12
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:27
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config RISCV_SOC_INTERRUPT_INIT
bool
default y
depends on SOC_SERIES_RISCV_VIRT
At <Zephyr>/arch/riscv/Kconfig:99
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:39
→ <Zephyr>/arch/Kconfig:12
Menu path: (Top) → RISCV Options → RISCV Processor Options
config RISCV_SOC_INTERRUPT_INIT
bool "Enable SOC-based interrupt initialization"
depends on RISCV
help
Enable SOC-based interrupt initialization
(call soc_interrupt_init, within _IntLibInit when enabled)
(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)