Help¶

PLL divisor, allowed values: 1-63.

Direct dependencies¶

CLOCK_STM32_PLL3_ENABLE && SOC_SERIES_STM32H7X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL

(Includes any dependencies from ifs and menus.)

Default¶

32

Kconfig definition¶

At <Zephyr>/drivers/clock_control/Kconfig.stm32h7:116

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25 → <Zephyr>/drivers/clock_control/Kconfig.stm32:153

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control → Enable PLL3

config CLOCK_STM32_PLL3_M_DIVISOR
    int "PLL3 divisor"
    range 1 63
    default 32
    depends on CLOCK_STM32_PLL3_ENABLE && SOC_SERIES_STM32H7X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      PLL divisor, allowed values: 1-63.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)