Software/Hardware controlled TWI Master driver.
- Features supported
- Repeated start
- No multi-master
- Only 7-bit addressing
- Supports clock stretching (with optional SMBus style slave timeout using software driver)
- Tries to handle slaves stuck in the middle of transfer
- Documentation specific to HW controlled TWI master driver.
Code snippet below illustrates the write sequence of the HW controlled TWI master driver.
while (true)
{
while (NRF_TWI1->EVENTS_TXDSENT == 0 && NRF_TWI1->EVENTS_ERROR == 0 && (--timeout))
{
}
if (timeout == 0 || NRF_TWI1->EVENTS_ERROR != 0)
{
NRF_TWI1->EVENTS_ERROR = 0;
NRF_TWI1->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
NRF_TWI1->POWER = 0;
nrf_delay_us(5);
NRF_TWI1->POWER = 1;
NRF_TWI1->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
return false;
}
NRF_TWI1->EVENTS_TXDSENT = 0;
if (--data_length == 0)
{
break;
}
NRF_TWI1->TXD = *data++;
}
Code snippet below illustrates the read sequence of the HW controlled TWI master driver.
while (true)
{
while (NRF_TWI1->EVENTS_RXDREADY == 0 && NRF_TWI1->EVENTS_ERROR == 0 && (--timeout))
{
}
NRF_TWI1->EVENTS_RXDREADY = 0;
if (timeout == 0 || NRF_TWI1->EVENTS_ERROR != 0)
{
NRF_TWI1->EVENTS_ERROR = 0;
NRF_TWI1->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
NRF_TWI1->POWER = 0;
nrf_delay_us(5);
NRF_TWI1->POWER = 1;
NRF_TWI1->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
return false;
}
*data++ = NRF_TWI1->RXD;
if (--data_length == 1)
{
NRF_PPI->CH[0].TEP = (uint32_t)&NRF_TWI1->TASKS_STOP;
}
if (data_length == 0)
{
break;
}
nrf_delay_us(20);
NRF_TWI1->TASKS_RESUME = 1;
}
- Documentation specific to SW controlled TWI master driver.
Code snippet below illustrates the write sequence of the SW controlled TWI master driver.
for (uint_fast8_t i = 0x80; i != 0; i >>= 1)
{
if (databyte & i)
{
}
else
{
}
if (!twi_master_wait_while_scl_low())
{
transfer_succeeded = false;
break;
}
}
Code snippet below illustrates the read sequence of the SW controlled TWI master driver.
for (uint_fast8_t i = 0x80; i != 0; i >>= 1)
{
if (!twi_master_wait_while_scl_low())
{
transfer_succeeded = false;
break;
}
{
byte_read |= i;
}
else
{
}
}