Vendor: GigaDevice Semiconductor


The GD32 pin controller (AF model) is a singleton node responsible for
controlling pin function selection and pin properties. For example, you can
use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
on the pin.

The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this:

  &pinctrl {
          /* your modifications go here */

All device pin configurations should be placed in child nodes of the
'pinctrl' node, as shown in this example:

  /* You can put this in places like a board-pinctrl.dtsi file in
   * your board directory, or a devicetree overlay in your application.

  /* include pre-defined combinations for the SoC variant used by the board */
  #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>

  &pinctrl {
    /* configuration for the usart0 "default" state */
    usart0_default: usart0_default {
      /* group 1 */
      group1 {
        /* configure PA9 as USART0 TX and PA11 as USART0 CTS */
        pinmux = <USART0_TX_PA9>, <USART0_CTS_PA11>;
      /* group 2 */
      group2 {
        /* configure PA10 as USART0 RX and PA12 as USART0 RTS */
        pinmux = <USART0_RX_PA10>, <USART0_RTS_PA12>;
        /* both PA10 and PA12 have pull-up enabled */

    /* configuration for the usart0 "sleep" state */
    usart0_sleep: usart0_sleep {
      /* group 1 */
      group1 {
        /* configure PA9, PA10, PA11 and PA12 in analog mode */
        pinmux = <ANALOG_PA9>, <ANALOG_PA10>, <ANALOG_PA12>, <ANALOG_PA11>;

The 'usart0_default' child node encodes the pin configurations for a
particular state of a device; in this case, the default (that is, active)
state. Similarly, 'usart0_sleep' child node encodes the pin configurations
for the sleep state (used in device low power mode). Note that analog mode
is used for low power states because it disconnects the pin pull-up/down
resistor, schmitt trigger, and output buffer.

As shown, pin configurations are organized in groups within each child node.
Each group can specify a list of pin function selections in the 'pinmux'

A group can also specify shared pin properties common to all the specified
pins, such as the 'bias-pull-up' property in group 2. Here is a list of
supported standard pin properties:

- drive-push-pull: Push-pull drive mode (default, not required).
- drive-open-drain: Open-drain drive mode.
- bias-disable: Disable pull-up/down (default, not required).
- bias-pull-up: Enable pull-up resistor.
- bias-pull-down: Enable pull-down resistor.
- slew-rate: Set the maximum speed (and so the slew-rate) of the output
  signal (default: 2MHz).

Note that drive and bias options are mutually exclusive.

To link pin configurations with a device, use a pinctrl-N property for some
number N, like this example you could place in your board's DTS file:

   #include "board-pinctrl.dtsi"

   &usart0 {
         pinctrl-0 = <&usart0_default>;
         pinctrl-1 = <&usart0_sleep>;
         pinctrl-names = "default", "sleep";


Top level properties

These property descriptions apply to “gd,gd32-pinctrl-af” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.


Grandchild node properties






Set the maximum speed of a pin. This setting effectively limits the
slew rate of the output signal. Defaults to "max-speed-2mhz", the SoC

Default value: max-speed-2mhz

Legal values: 'max-speed-2mhz', 'max-speed-25mhz', 'max-speed-50mhz', 'max-speed-200mhz'



An array of pins sharing the same group properties. The pins should
be defined using pre-defined macros or, alternatively, using the
GD32_PINMUX_AF or GD32_PINMUX_AFIO utility macros depending on the
pinmux model used by the SoC series.

This property is required.



disable any pin bias



enable pull-up resistor



enable pull-down resistor



drive actively high and low



drive with open drain (hardware AND)