:orphan:
.. raw:: html
.. dtcompatible:: st,stm32-dma-v2bis
.. _dtbinding_st_stm32_dma_v2bis:
st,stm32-dma-v2bis
##################
Vendor: :ref:`STMicroelectronics `
Description
***********
These nodes are "dma" bus nodes.
.. code-block:: none
STM32 DMA controller (V2bis) for the stm32F0, stm32F1 and stm32L1 soc families
This DMA controller includes several channels with different requests.
All the requests ar ORed before entering the DMA, so that only one request
must be enabled at a time.
DMA clients connected to the STM32 DMA controller must use the format
described in the dma.txt file, using a 2-cell specifier for each
channel: a phandle to the DMA controller plus the following four integer cells:
1. channel: the dma stream from 1 to
2. channel-config: A 32bit mask specifying the DMA channel configuration
A name custom DMA flags for channel configuration is used
which is device dependent see stm32_dma.h:
-bit 5 : DMA cyclic mode config
0x0: STM32_DMA_MODE_NORMAL
0x1: STM32_DMA_MODE_CYCLIC
-bit 6-7 : Direction (see dma.h)
0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM
0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH
0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
0x3: reserved for PERIPH to PERIPH
-bit 9 : Peripheral Increment Address
0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
0x1: STM32_DMA_PERIPH_INC: increment address between transfers
-bit 10 : Memory Increment Address
0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
0x1: STM32_DMA_MEM_INC: increment address between transfers
-bit 11-12 : Peripheral data size
0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits)
0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
0x3: reserved
-bit 13-14 : Memory data size
0x0: STM32_DMA_MEM_8BITS: Byte (8 bits)
0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
0x3: reserved
-bit 15: Reserved
-bit 16-17 : Priority level
0x0: STM32_DMA_PRIORITY_LOW: low
0x1: STM32_DMA_PRIORITY_MEDIUM: medium
0x2: STM32_DMA_PRIORITY_HIGH: high
0x3: STM32_DMA_PRIORITY_VERY_HIGH: very high
Example of dma usual combination for peripheral transfer
#define STM32_DMA_PERIPH_TX (STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC)
#define STM32_DMA_PERIPH_RX (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC)
Example of dma node for stm32f103
dma1: dma-controller@40020400 {
compatible = "st,stm32-dma-v2bis";
...
dma-requests = <7>;
status = "disabled";
};
For the client part, example for stm32f103 on DMA1 instance
Tx using channel 3
Rx using channel 2
spi1 {
compatible = "st,stm32-spi";
dmas = <&dma1 3 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
<&dma1 2 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
dma-names = "tx", "rx";
};
Properties
**********
.. tabs::
.. group-tab:: Node specific properties
Properties not inherited from the base binding file.
.. list-table::
:widths: 1 1 4
:header-rows: 1
* - Name
- Type
- Details
* - ``#dma-cells``
- ``int``
- .. code-block:: none
Number of items to expect in a DMA specifier
This property is **required**.
Constant value: ``2``
* - ``st,mem2mem``
- ``boolean``
- .. code-block:: none
If the DMA controller V1 supports memory to memory transfer
* - ``dma-offset``
- ``int``
- .. code-block:: none
offset in the table of channels when mapping to a DMAMUX
for 1st dma instance, offset is 0,
for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
for 3rd dma instance, offset is the nb of dma channels of the 2nd dma
plus the nb of dma channels of the 1st dma instance, etc.
* - ``dma-channel-mask``
- ``int``
- .. code-block:: none
Bitmask of available DMA channels in ascending order that are
not reserved by firmware and are available to the
kernel. i.e. first channel corresponds to LSB.
* - ``dma-channels``
- ``int``
- .. code-block:: none
Number of DMA channels supported by the controller
* - ``dma-requests``
- ``int``
- .. code-block:: none
Number of DMA request signals supported by the controller.
* - ``dma-buf-addr-alignment``
- ``int``
- .. code-block:: none
Memory address alignment requirement for DMA buffers used by the controller.
* - ``dma-buf-size-alignment``
- ``int``
- .. code-block:: none
Memory size alignment requirement for DMA buffers used by the controller.
* - ``dma-copy-alignment``
- ``int``
- .. code-block:: none
Minimal chunk of data possible to be copied by the controller.
.. group-tab:: Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
.. group-tab:: Base properties
Properties inherited from the base binding file, which defines
common properties that may be set on many nodes. Not all of these
may apply to the "st,stm32-dma-v2bis" compatible.
.. list-table::
:widths: 1 1 4
:header-rows: 1
* - Name
- Type
- Details
* - ``reg``
- ``array``
- .. code-block:: none
register space
This property is **required**.
See :ref:`dt-important-props` for more information.
* - ``interrupts``
- ``array``
- .. code-block:: none
interrupts for device
This property is **required**.
See :ref:`dt-important-props` for more information.
* - ``status``
- ``string``
- .. code-block:: none
indicates the operational status of a device
Legal values: ``'ok'``, ``'okay'``, ``'disabled'``, ``'reserved'``, ``'fail'``, ``'fail-sss'``
See :ref:`dt-important-props` for more information.
* - ``compatible``
- ``string-array``
- .. code-block:: none
compatible strings
This property is **required**.
See :ref:`dt-important-props` for more information.
* - ``reg-names``
- ``string-array``
- .. code-block:: none
name of each register space
* - ``interrupts-extended``
- ``compound``
- .. code-block:: none
extended interrupt specifier for device
* - ``interrupt-names``
- ``string-array``
- .. code-block:: none
name of each interrupt
* - ``interrupt-parent``
- ``phandle``
- .. code-block:: none
phandle to interrupt controller node
* - ``label``
- ``string``
- .. code-block:: none
Human readable string describing the device (used as device_get_binding() argument)
See :ref:`dt-important-props` for more information.
This property is **deprecated**.
* - ``clocks``
- ``phandle-array``
- .. code-block:: none
Clock gate information
* - ``clock-names``
- ``string-array``
- .. code-block:: none
name of each clock
* - ``#address-cells``
- ``int``
- .. code-block:: none
number of address cells in reg property
* - ``#size-cells``
- ``int``
- .. code-block:: none
number of size cells in reg property
* - ``dmas``
- ``phandle-array``
- .. code-block:: none
DMA channels specifiers
* - ``dma-names``
- ``string-array``
- .. code-block:: none
Provided names of DMA channel specifiers
* - ``io-channels``
- ``phandle-array``
- .. code-block:: none
IO channels specifiers
* - ``io-channel-names``
- ``string-array``
- .. code-block:: none
Provided names of IO channel specifiers
* - ``mboxes``
- ``phandle-array``
- .. code-block:: none
mailbox / IPM channels specifiers
* - ``mbox-names``
- ``string-array``
- .. code-block:: none
Provided names of mailbox / IPM channel specifiers
* - ``wakeup-source``
- ``boolean``
- .. code-block:: none
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
* - ``power-domain``
- ``phandle``
- .. code-block:: none
Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
* - ``zephyr,pm-device-runtime-auto``
- ``boolean``
- .. code-block:: none
Automatically configure the device for runtime power management after the
init function runs.
Specifier cell names
********************
- dma cells: channel, channel-config