Architecture of nRF54H20

The nRF54H20 is a multicore System-on-Chip (SoC) that uses an asymmetric multiprocessing (AMP) configuration. Each core is tasked with specific responsibilities, and is optimized for different workloads.

The following documents introduce the architecture of the nRF54H20 SoC:

• The Introduction to nRF54H20 PDF document, providing an overview of the hardware and software features of the nRF54H20.

• The nRF54H20 Objective Product Specification 0.3.1 (OPS) PDF document.

• The nRF54H20 prototype difference PDF document, listing the major differences between the final and the prototype silicon provided on the nRF54H20 PDK.

The following pages briefly describe topics like the responsibilities of the cores, their interprocessor interactions, the memory mapping, and the boot sequence in the nRF54H20 SoC.

Subpages:

• nRF54H20 Domains
  • Application Core
  • Radio Core
  • Global Domain
  • Secure Domain
  • System Controller
  • Cores management
• nRF54H20 Memory Layout
  • RAM
  • MRAM (non-volatile memory)
  • Memory Privilege Controller (MPC) configuration
  • SAU configuration
• Interprocessor Communication in nRF54H20
  • Technical solution
  • IPC connections scheme
• nRF54H20 Boot Sequence
  • Cold Boot Sequence
  • Boot stages
• nRF54H20 lifecycle states